Decimation Filter
28-32
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
•
Overrun in enhanced debug monitor, flagged by DECFILT_x_MSR[DIVR]
•
Integrator overrun, flagged by DECFILT_x_MSR[SVR]
•
Integrator value exception, flagged by DECFILT_x_MSR[SSE]
•
Integrator count exception, flagged by DECFILT_x_MSR[SCE]
A filter overflow occurs when the two’s-complement result value from the MAC accumulator is out of the
range of values that can be stored in tap register 4 (IIR) or in the output register.
An input overrun occurs when the input buffer is holding a word of input data and one more word of data
is received by the filter. See
Section 28.3.1.1, Input Buffer Overrun
An output overrun occurs when a new word of data is sent to the output buffer but the previous word of
data has not been handled yet. See
Section 28.3.2.1, Output Buffer Overrun
, for more details.
These flags can be set for input from or output to an eQADC, however they are only cleared by
•
the CPU, or
•
by the soft reset command (DECFILT_x_MCR[SRES]
•
by the clear flag bits in the DECFILT_x_MSR register.
The DMA function for integrator result, input and output buffers is enabled setting the
DECFILT_x_MCR[DSEL] = 1. The DMA request generally replaces the interrupt request that is normally
generated by these registers/conditions and is discussed in more detail in
Section 28.3.12.1.3, Input Buffer
Section 28.3.12.2.2, Output Buffer DMA Request
.
28.3.12.1 Input Buffer Interrupt and DMA Requests
28.3.12.1.1
Input Buffer Interrupt
This interrupt is enabled by the DECFILT_x_MCR[IBIE] bit and is asserted only when
DECFILT_x_MCR[DSEL] = 0. If DECFILT_x_MCR[DSEL] = 1, a DMA request is generated instead
(See
Section 28.3.12.1.3, Input Buffer DMA Request
). When this request is asserted, the
DECFILT_x_MSR[IBIF] bit is set to indicate a pending interrupt.
When the input data source is the CPU, the input buffer interrupt request is asserted when the input buffer
is empty, meaning the block is requesting data be written into the input buffer. The interrupt request is
cleared when the CPU writes a one to the DECFILT_x_MSR[IBIC] bit, or by a soft reset command.
28.3.12.1.2
Input Buffer Enhanced Debug Monitor Interrupt
When the input data source is an eQADC, DMA is disabled, and enhanced debug is enabled, the input
sample data can be read by the CPU when this interrupt request is asserted. The interrupt is asserted when
a new word of sample data is supplied to the filter, and gives the application visibility into the input data
being from an eQADC.
In enhanced debug mode, if the input buffer is overwritten by the next word of sample data, an input read
overrun event can occur (the DECFILT_x_MSR[DIVR] bit is asserted) if the interrupt request is not
cleared before, or at the same time as, the new sample arrives to set the interrupt. The
Summary of Contents for PXR4030
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