Decimation Filter
Freescale Semiconductor
28-35
PXR40 Microcontroller Reference Manual, Rev. 1
28.3.13.2 Integrator Output
The integrator output is provided in two separate 32 bit registers: DECFILTER_FINTVAL and
DECFILTER_CINTVAL. DECFILTER_FINTVAL is only updated when an output request is made by an
eTPU2 channel or by a core or DMA access to a configuration register. DECFILTER_CINTVAL is
updated whenever a new integration result is available or when a reset request is made by hardware or
software. The output is in one of two forms:
•
the 32-bit, fixed point unsigned accumulation of the absolute values from the filter output, when
configured for absolute operation (DECFILTER_MXCR[SSIG] = 0). This allows a total of 131071
samples to be integrated before an overflow occurs.
•
the 32-bit, fixed point signed two’s complement accumulation of the signed values from the filter
output, when configured for signed operation (DECFILTER_MXCR[SSIG] = 1). This allows a
total of 65536 samples to be integrated before an overflow occurs
The fractional part of the accumulation is 15 bits wide in both forms.
An accumulation overflow is flagged in DECFILTER_MXSR[SSOVF] when an output request occurs.
The accumulator can overflow in either of the ways described below, selected through the
DECFILTER_MXCR[SSAT]:
•
saturated accumulation (SSAT=1), so that an overflow results in the value of 0xFFFFFFFF for
absolute value accumulation (SSIG=0), or 0x7FFFFFFF (positive) and 0x80000000 (negative) for
signed accumulation (SSIG=1).
•
non-saturated accumulation (SSAT=0), so that an overflow results in the modulo 2
17
accumulation
value. This operation is only allowed in absolute accumulation (SSIG=0).
NOTE
A non-saturated overflow that occurs before SSOVF is cleared is still
flagged in the next output request.
The integrator output value becomes available in register DECFILTER_FINTVAL (see
Decimation Filter Final Integration Value Register (DECFILT_x_FINTVAL)
request is issued. The integrator output request can be issued in the following ways:
•
by an eTPU2 channel; the enabling and selection of the signal request modes is done through the
DECFILTER_MXCR[SRQSEL] field (see
Section 28.2.2.3, Decimation Filter Module Extended
Configuration Register (DECFILT_x_MXCR)
), and the channel selection is done through the
ZSELn fields of SIU_DECFIL1 and SIU_DECFIL2 and SIU_DECFIL3 registers in the SIU
module.
•
by software, writing 1 to the DECFILTER_MXCR[SRQ];
The integrator output request also updates the register DECFILTER_FINTCNT, which holds the number
of samples accumulated into the register DECFILTER_FINTVAL. This accumulated sample counter can
operate either in a saturated or “wrapped” count mode, as selected by DECFILTER_MXCR[SCSAT]. In
both cases, a counter overflow is flagged by DECFILTER_MXSR[SCOVF].
NOTE
A non-saturated overflow that occurs before an SCOVF clear is still flagged
in the next output request.
Summary of Contents for PXR4030
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