Decimation Filter
28-36
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
An integrator output update can also issue a DMA or interrupt request. The interrupt and DMA requests
are the same ones used for the filter output buffer (see
Section 28.3.12.2, Output Buffer Interrupt and DMA
Section 28.3.12.1.3, Input Buffer DMA Request
). DECFILTER_MCR[SDIE] is used to
enable integrator interrupts, and the DECFILTER_MXCR[SDMAE] enables the DMA integrator requests.
The integrator DMA request uses the same signal as the filter output DMA request, so one must never use
any configuration that allows both the integrator and filter output to make DMA requests.
Integrator output updates are flagged by DECFILTER_MXSR[SDF]. The integrator overrun is detected in
the same way as a filter output buffer overrun, and is flagged by DECFILTER_MXSR[SVR]. An
integrator overrun also generates an error interrupt if DECFILTER_MCR[ERREN] = 1 (see
Section 28.3.2.1, Output Buffer Overrun
Registers DECFILTER_CINTVAL and DECFILTER_CINTCNT provide a way to poll intermediate
integration values and sample counts, respectively (see
Section 28.2.2.12, Decimation Filter Current
Integration Value Register (DECFILT_x_CINTVAL)
, and
Section 28.2.2.13, Decimation Filter Current
Integration Count Value Register (DECFILT_x_CINTCNT)
). DECFILTER_CINTVAL is updated
whenever the integrator is reset or a new sample is accumulated. DECFILTER_CINTCNT is updated only
when DECFILTER_CINTVAL is read, so that coherency between the value and count values is
guaranteed. Therefore, the read access order of that pair of registers must be DECFILTER_CINTVAL first,
followed by DECFILTER_CINTCNT.
NOTE
The flags SSOVF and SCOVF can also asserted when
DECFILTER_CINTVAL is read. The SSOVF and SCOVF set and clearing
rules apply for the DECFILTER_CINTVAL read the same way as for an
integrator output request.
28.3.13.3 Integrator Reset
The integration value is reset to the value of zero, in the following ways:
•
by hardware: on hardware reset, or controlled by an eTPU2 channel; the enabling and selection of
the zero signal modes is done through DECFILTER_MXCR[SZROSEL] (see
Decimation Filter Module Extended Configuration Register (DECFILT_x_MXCR)
channel selection is defined by the ZSELn fields of the SIU_DECFIL1 and SIU_DECFIL2 and
SIU_DECFIL3 registers in the SIU module.
•
by software: on software reset, or writing 1 to the DECFILTER_MXCR bit SZRO;
The integrator reset also zeroes the internal counter of accumulated samples and the internal overflow state
(but not SSOVF and SCOVF). Software and hardware reset resets all integrator registers immediately.
An Integrator zero command from an eTPU2 channel or by software (SZRO) affects the integrator
registers and flags as follows:
•
DECFILTER_CINTVAL resets immediately;
•
DECFILTER_CINTCNT does not reset immediately; it is updated only upon a
DECFILTER_CINTVAL read, loaded with the number of integrated samples occurred after the
reset;
Summary of Contents for PXR4030
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