Enhanced Time Processing Unit (eTPU2)
29-10
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
29.1.2.2
eTPU Enhancements over TPU3
•
32 orthogonal channels with enhanced functionality. Full support for double action with double
match and double transition sub-mode combinations.
•
Input and Output features separated in channel logic and microinstructions, allowing input and
output signals to be processed separately or combined.
•
Increased time resolution and execution unit to 24 bits.
•
Increased linear code memory, shared by two eTPU Engines, configurable up to 16K positions (64
Kbytes).
•
Increased SDM address range (8 Kbytes each Engine) and width (32 bits per parameter). The SDM
can be dynamically allocated to support variable number of parameters for each channel. Each
channel can have access to at least 256 parameters.
•
The SDM is fully shared by two eTPU Engines (SDM), supporting direct inter-engine
communication with the help of hardware semaphores.
•
Enhanced arithmetic operations, including add/subtract with carry, absolute value, multiple shift
and rotate, conditional execution with variable operand widths.
•
Enhanced logic operations, including bitwise operations (and, or, xor) and bit manipulation, with
conditional execution. Support for read-modify-write of any bit in the SDM.
•
Hardware for Multiply/MAC/Divide, running in parallel to execution of other operations. The
24-bit divide result is available after 13 other unrelated instructions. Multiplication supports any
data width of both operands (8, 16 or 24 bits), signed or unsigned. A 24x24 Multiply/MAC result
is available after four other unrelated instructions. A 24x8 Multiply/MAC result is available after
one other unrelated instruction.
•
Supports export/import of time bases from other sources through the real time bus (STAC - Shared
Time and Counter bus). This internal bus is used for sharing real time data between multiple
peripherals.
•
Contains angle clock hardware, supported by microcode, which can provide a 24-bit angle bus
instead of time bus. This feature enables the eTPU to run angle based engine control applications.
•
More interrupt types. Each eTPU channel can generate a data transfer request interrupt, in addition
to regular interrupts, and one global exception interrupt. Data Transfer requests can be used either
as interrupt sources or DMA requests. This feature takes advantage of DMA peripherals which
off-load the Host. Interrupt Overflow status is also provided.
•
Improved visibility to the Host (pin states, time bases, serviced channel).
•
An edge case of priority inversion on TPU3 Scheduler was resolved.
•
Supports channel link requests between eTPU Engines.
29.1.2.3
eTPU2 Enhancements over eTPU
•
TCR1, channel logic and digital filters (both channel and TCRCLK) now have an option to run at
divisions of full system clock speed, besides eTPU clock / 2.
•
Channels support unordered transitions: transition B can now be detected before transition A.
Related to this enhancement, TDLA and TDLB can now be independently negated by microcode.
Refer to the
eTPU Reference Manual
for details.
Summary of Contents for PXR4030
Page 1: ...PXR40 Microcontroller Reference Manual Devices Supported PXR4030 PXR4040 PXR40RM Rev 1 06 2011...
Page 30: ...PXR40 Microcontroller Reference Manual Rev 1 Freescale Semiconductor xxx...
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Page 66: ...Memory Map PXR40 Microcontroller Reference Manual Rev 1 2 4 Freescale Semiconductor...
Page 120: ...Signal Descriptions 3 54 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...
Page 860: ...FlexCAN Module 24 50 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...
Page 1167: ...Decimation Filter Freescale Semiconductor 28 53 PXR40 Microcontroller Reference Manual Rev 1...
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