Enhanced Time Processing Unit (eTPU2)
Freescale Semiconductor
29-13
PXR40 Microcontroller Reference Manual, Rev. 1
Module Disable Mode is entered by setting ETPUECR register bit MDIS. eTPU Engines can be
individually stopped going into Module Disable Mode (there is one ETPUECR register for each Engine).
Each engine can leave Module Disable Mode by writing MDIS=0 (which can only be done if VIS=0).
Stop Mode is activated by IP-Bus (device stop request). In this case, the eTPU waits for both eTPU
Engines to enter in stop mode, and then asserts the stop acknowledge line. eTPU leaves Stop Mode when
device stop request is negated, but only if VIS=0. If device stop request is negated and VIS=1, eTPU will
leave Stop Mode as soon as VIS=0.
NOTE
An Engine can stay in Module Disable mode when it leaves Stop Mode if
its bit MDIS=1, even if the other leaves it.
29.2
External Signal Description
29.2.1
Overview
There are 69 external signals associated with each eTPU Engine: 32 channel input signals, 32 channel
output signals, 4 output disable inputs, and TCRCLK clock input, totalling 138 in a Dual Engine system.
The TCRCLK signal is used to clock TCR1/2 counters or gate the TCR2 clock. In Angle Mode it is used
as tooth signal input.
29.2.2
Detailed Signal Descriptions
29.2.2.1
eTPU Channel Output Signals [0-31]
Each channel output signal is associated with a channel. The microcode may affect the logic level of an
output signal
1
by implementing one of two actions:
•
Specify the logic level output to the signal when there is a match or a transition.
•
Immediately force a logic level.
The output signal may also be forced to a logic level, independently of the output value from the channel
logic, by one of the four (each Engine) output disable signals (see
Section 29.2.2.4, eTPU Channel Output
).
29.2.2.2
eTPU Channel Input Signals [0-31]
Each channel input signal is associated with a channel. The microcode can directly control the effect of the
transition edge. Each channel can be programmed to sense a transition when a rising and/or falling edge
is detected. The channel logic can also process two transition events, and relate these events to each other
and to other programmed timer events. The edge sensitivities of the two transition events are configured
independently by microcode.
1.
Note that the minimum pulse width is one microcycle (two eTPU clocks), and slow 5V pads may not be able to transfer it
on time. For generation of very short pulses the eTPU pads have to be programmed by the system integration for fast
operation mode with the voltage levels defined for fast pad operation in the MCU technology.
Summary of Contents for PXR4030
Page 1: ...PXR40 Microcontroller Reference Manual Devices Supported PXR4030 PXR4040 PXR40RM Rev 1 06 2011...
Page 30: ...PXR40 Microcontroller Reference Manual Rev 1 Freescale Semiconductor xxx...
Page 40: ...PXR40 Microcontroller Reference Manual Rev 1 xl Freescale Semiconductor...
Page 66: ...Memory Map PXR40 Microcontroller Reference Manual Rev 1 2 4 Freescale Semiconductor...
Page 120: ...Signal Descriptions 3 54 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...
Page 860: ...FlexCAN Module 24 50 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...
Page 1167: ...Decimation Filter Freescale Semiconductor 28 53 PXR40 Microcontroller Reference Manual Rev 1...
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