Resets
PXR40 Microcontroller Reference Manual, Rev. 1
4-2
Freescale Semiconductor
The Reset Status Register (SIU_RSR) gives the source, or sources, of the last reset and indicates whether
a glitch has occurred on the RESET pin. The SIU_RSR is updated for all reset sources except JTAG reset.
All reset sources initiate execution of the Boot Assist Module (BAM) program with the exception of the
Software External Reset.
The Reset Configuration Half Word (RCHW) determines the MCU configuration after reset. The RCHW
is stored in internal flash, or a default configuration is used. During reset, the RCHW is read from internal
flash memory. The BOOTCFG[0:1]
1
Chapter 7, System Integration Unit (SIU)
.
The
BAM program reads the value of the BOOTCFG[0:1] pins from the BOOTCFG field of the SIU_RSR,
then reads the RCHW from the specified location, and then uses the RCHW value to determine and
execute the specified boot procedure. Note: the reset controller latches the value on the BOOTCFG input
to the SIU 4 clock cycles prior to the negation of RSTOUT.
4.2
Reset Vector
The reset vector for this device is 0xFFFF_FFFC. This is a fixed location in the BAM. The BAM program
executes after every internal reset. The BAM program determines where to branch after its execution
completes based on the value on the BOOTCFG[0:1] pins. See the BAM chapter’s functional description
for details on the BAM program operation and branch location to application software.
4.3
Reset Pins
4.3.1
RESET
The RESET pin is an active low input. The RESET pin must be asserted by an external device during a
power-on or whenever an external reset is required. The internal reset signal asserts only if the RESET pin
asserts for 10 clock cycles. Assertion of the RESET pin while the reset state machine is already processing
a reset causes the reset cycle to start over. The RESET pin has a glitch detector which detects spikes greater
than 2 clocks in duration that fall below the switch point of the input buffer logic of the VDDEH input
Table 4-2. PLLCFG Options
Package Pins
1
Clock Mode
PLLCFG[0]
PLLCFG[1]
0
0
PLL Off mode
0
1
Normal mode with external reference
1
0
Normal mode with crystal reference
1
1
Reserved
1
The PLLCFG[2] pin configures the crystal oscillator range:
PLLCFG[2] = 0, for 8 MHz to 20 MHz
PLLCFG[2] = 1, for 40 MHz
1. BOOTCFG[0] is not available on all packages.
Summary of Contents for PXR4030
Page 1: ...PXR40 Microcontroller Reference Manual Devices Supported PXR4030 PXR4040 PXR40RM Rev 1 06 2011...
Page 30: ...PXR40 Microcontroller Reference Manual Rev 1 Freescale Semiconductor xxx...
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Page 120: ...Signal Descriptions 3 54 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...
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