Enhanced Time Processing Unit (eTPU2)
29-64
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
29.3.4.2.1
CDC Programming
The Coherent Dual-parameter Controller Register (see
Section 29.2.5.2, ETPUCDCR - eTPU Coherent
Dual-Parameter Controller Register
) is used to configure and initiate CDC transfers between the
temporary area and channel parameter area. Host asserts STS bit in order to start the data transfer. CDC
then contends for the SDM and starts the transfer. When the data transfer is complete, STS returns to 0.
Host receives wait-states for writing STS=1 while CDC contends for SDM and during the transfer. The
write access ends when CDC finishes the transfer. Host receives wait-states during the CDC transfer. If
Host writes ETPUCDCR with STS=0 or does not write the STS byte, the CDC transfer does not occur.
CDC programming can be summarized as follows:
1. If it is a write transfer, i.e., from Host to channel, write the two parameters into temporary area.
2. Write ETPUCDCR with STS=1 and the remaining CDC programming parameters: parameter
width (32 or 24 bits, field PWIDTH), transfer direction (read or write, field WR), temporary
parameter area base address (field PBBASE), and the absolute addresses of the parameters to be
transferred (concatenation of the fields CTBASE and PARM0/1).
3. If it is a read transfer, i.e., from channel to host, read the two parameters from the temporary area
into Host memory/registers.
29.3.4.3
SDM Arbitration
Up to four entities can access SDM:
•
two Microengines (in a dual eTPU Engine system)
•
the Coherent Dual-parameter Controller (CDC)
•
the Host CPU (direct memory-mapped access)
The following rules specify the access priorities for contended access. They keep compatibility with the
TPU3 dual parameter access atomicity, but only between the microengine and CDC (not Host accesses
through slave bus).
1. Microengine accesses from the two eTPU Engines are interleaved between each other, but not with
Host or CDC accesses;
2. The eTPU microengine(s) gives priority for SDM accesses to either the Host CPU or the CDC
under any of the following conditions:
a.
the microengine has completed accessing the second parameter in a back-to-back SDM
access
1
.
b.
the SDM was not accessed during the last arbitration slot for the microengine and the host does
not loose the access to the other engine in the current arbitration slot
2
.
c.
CDC is transferring data, after its first (read) access. Note that the CDC can be in middle of a
data transfer of another pair of parameters, unrelated to the ones that microengine tries to
access.
3. The eTPU microengine takes priority for SDM accesses under either of the following conditions:
1.
If microengine tries to access the SDM in the following microcycles, the third and fourth consecutive accesses are
considered the first and second of a new back-to-back dual access.
2.
The microengine access slot is between its own T4 and T2 edges.
Summary of Contents for PXR4030
Page 1: ...PXR40 Microcontroller Reference Manual Devices Supported PXR4030 PXR4040 PXR40RM Rev 1 06 2011...
Page 30: ...PXR40 Microcontroller Reference Manual Rev 1 Freescale Semiconductor xxx...
Page 40: ...PXR40 Microcontroller Reference Manual Rev 1 xl Freescale Semiconductor...
Page 66: ...Memory Map PXR40 Microcontroller Reference Manual Rev 1 2 4 Freescale Semiconductor...
Page 120: ...Signal Descriptions 3 54 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...
Page 860: ...FlexCAN Module 24 50 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...
Page 1167: ...Decimation Filter Freescale Semiconductor 28 53 PXR40 Microcontroller Reference Manual Rev 1...
Page 1168: ...Decimation Filter 28 54 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...
