Freescale Semiconductor PXR4030 Reference Manual Download

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Enhanced Time Processing Unit (eTPU2)

29-66

Freescale Semiconductor

PXR40 Microcontroller Reference Manual, Rev. 1

29.3.4.4.2

Three-Sample Mode

In this mode, like in the TPU2/3 mode, the EDF uses the filter clock as a sampling clock. The EDF
compares three consecutive samples. If all three samples have the same value, the input signal state is
updated.

The Three-Sample mode gives more signal latency than the Two-Sample mode, but also better noise
immunity and better ratio between minimum detected signal pulse to maximum filtered noise pulse. When
a certain filter clock frequency is selected for Two-sample mode, double filter clock frequency can be
selected to get better latency in Three-sample mode.

29.3.4.4.3

Continuous Mode

In this mode the EDF compares all the values sampled at the rate of eTPU clock divided by two, between
two consecutive filter clock pulses. If the signal is continuously stable for the entire digital filter clock
period (i.e all the samples have the same signal value), the input signal state is updated.

This method gives the same latency and the same ratio between minimum detected signal pulse to
maximum filtered noise pulse, as the Two-Sample mode, as long as there is no noise. Each sampled noise
delays the signal transition detection by at least a whole digital filter clock period.

The Continuous mode gives the best noise immunity by comparing multiple samples of the noise. On the
other hand, when a short noise pulse appears in the middle of the filter clock period at the same time of a
real signal transition, the Continuous mode may reject a real signal transition and delay the response to the
first filter clock period in which the signal is continuously stable. This may add to the latency and also to
the minimum detected signal pulse in a noisy environment.

29.3.4.4.4

Bypass Mode

In bypass mode the signal that feeds the edge detection comes directly from the output of the synchronizer,
not filtered.

29.3.4.4.5

Filter Clock Prescaler

The TCRCLK signal and each channel configured as an input have an associated synchronizer followed
by a digital filter connected to the signal that samples signal transitions. After reset, the digital filter filters
out high and low pulse widths smaller than the period of two eTPU clocks with ETPUECR bit FCSS=0,
or 1 eTPU clock with FCSS=1, preventing these transitions from being input to the transition detect logic.
For FPSCK=0 and FCSS=0, the synchronizer and digital filter are guaranteed to pass pulses that are as
wide as or wider than four eTPU clocks, meaning a minimum period of 8 eTPU clocks. These figures are
halved by setting FCSS=1. By changing the FPSCK field in register ETPUECR the user can select a lower
clock rate for the filter signal to define wider valid pulses and filter out wider noise pulses. The filter
prescaler clock control is a division of the eTPU clock. To guarantee pulse detection by the digital filter,
the pulse must cover at least the stated number of samples at the filter clock rate. For example, a two
sample digital filter must sample two points in the pulse to detect it.

Table 29-19

shows the minimum

guaranteed detected pulse width and the maximum filtered noise pulse width. The table refers only to the
digital filter operation. The external pulses may have to be wider (to ensure detection) or narrower (to
ensure filtering) depending on the rise/fall delay differences in the MCU receivers and internal logic.

Freescale Semiconductor PXR4030, Reference Manual

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