External Bus Interface (EBI)
30-8
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
D_TEA is asserted by the EBI when the internal bus monitor detected a timeout error.
Section 30.4.2.8, Termination Signals Protocol
for more details.
30.2.3.10 D_TS — Transfer Start
D_TS is asserted by the current bus owner to indicate the start of a transaction on the external bus.
D_TS is only asserted for the first clock cycle of the transaction, and is negated in the successive clock
cycles until the end of the transaction.
30.2.3.11 D_WE [0:3] — Write/Byte Enables 0-3
Write enables are used to enable program operations to a particular memory. These signals can also be used
as byte enables for read and write operation by setting the WEBS bit in the appropriate Base Register.
D_WE[0:3] are only asserted for chip-select accesses.
For chip-select accesses to a 16-bit port, only D_WE[0:1] are used by the EBI, regardless of which half of
the D_ADD_DAT bus is selected via the D16_31 bit in the EBI_MCR.
Section 30.4.1.11, Four Write/Byte Enable (D_WE) Signals
functionality.
30.2.4
Signal Output Buffer Enable Logic by Mode
describes how the EBI drives its output buffer enable (OBE) signals. These are internal signals
from the EBI to device logic outside the EBI, that determine when the EBI strongly drives values on pins.
When the OBE for an EBI signal is asserted (1), the EBI strongly drives the value on that pin. When the
OBE is negated (0), the EBI does not drive the signal, and the value is determined by internal or external
pullups/pulldowns, and/or device logic outside EBI block.
Table 30-4. Signal Output Buffer Enable Logic by Mode
1
Signal
OBE Value by Mode (1=strongly driven, 0=not driven by EBI)
Module Disable Mode
2
(MDIS=1)
Single Master Mode
(MDIS=0)
D_ADD[9:30]
0
1
D_BDIP
0
1
CAL_CS[0:3]
0
1
D_ADD_DAT[0:31]
0
Only 1 during write access or on
Address phase when Addr/Data
muxing is enabled.
D_OE
0
1
D_RD_WR
0
1
Summary of Contents for PXR4030
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