External Bus Interface (EBI)
Freescale Semiconductor
30-11
PXR40 Microcontroller Reference Manual, Rev. 1
30.3.1.2
EBI Transfer Error Status Register (EBI_TESR)
The EBI Transfer Error Status Register contains a bit for each type of transfer error on the external bus. A
bit set to logic 1 indicates what type of transfer error occurred since the last time the bits were cleared.
Each bit can be cleared by reset or by writing a 1 to it. Writing a 0 has no effect. This register cannot be
written when the MDIS bit is set in the EBI_MCR.
25
MDIS
Module Disable Mode
The MDIS bit controls an internal EBI "enable clk" signal which can be used (if MCU logic supports) to control the
clocks to the EBI. The MDIS bit allows the clock to be stopped to the non-memory mapped logic in the EBI, effectively
putting the EBI in a software controlled power-saving state. See Section 29.1.4.3, “Module Disable Mode for more
information. No external bus accesses can be performed when the EBI is in Module Disable Mode (MDIS=1).
0 Module Disable Mode is inactive (assert "enable clk" signal)
1 Module Disable Mode is active (negate "enable clk" signal)
26-28
Reserved
29
D16_31
Data Bus 16_31 Select
The D16_31 bit controls whether the EBI uses the D_ADD_DAT[0:15] or D_ADD_DAT[16:31] signals, when in 16-bit
Data Bus Mode (DBM=1) or for chip-select accesses to a 16-bit port (PS=1). For systems using A/D muxing with a
16-bit port, it is recommended to set D16_31 to 1.
0 D_ADD_DAT[0:15] signals are used for 16-bit port accesses
1 D_ADD_DAT[16:31] signals are used for 16-bit port accesses
30
AD_MUX
Address on Data Bus Multiplexing Mode
The AD_MUX bit controls whether non-chip-select accesses have the address driven on the data bus in the address
phase of a cycle.
0 Only Data on data pins for non-CS accesses.
1 Address on Data Multiplexing Mode is used for non-CS accesses.
31
DBM
Data Bus Mode
The DBM bit controls whether the EBI is in 32-bit or 16-bit Data Bus Mode.
0 32-bit Data Bus Mode is used
1 16-bit Data Bus Mode is used
Offset: E0x8
Access: User read
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TEAF BMTF
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 30-3. EBI Transfer Error Status Register (EBI_TESR)
Table 30-6. EBI_MCR Field Descriptions (continued)
Field
Description
Summary of Contents for PXR4030
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