External Bus Interface (EBI)
30-20
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
NOTE
The exception to the preceding D_WE description is that for 16-bit port
transfers (DBM=1 or PS=1), only the D_WE[0:1] signals are used,
regardless of whether D_ADD_DAT[0:15] or D_ADD_DAT[16:31] are
selected (via the D16_31 bit in the EBI_MCR). This means for the case
where D_ADD_DAT[16:31] are selected, that WE0 indicates that
D_ADD_DAT[16:23] contains valid data, and WE1 indicates that
D_ADD_DAT[24:31] contains valid data.
The Write/Byte Enable lines affected in a transaction for a 32-bit port (PS = 0) and a 16-bit port (PS=1)
are shown in
. Only Big Endian byte ordering is supported by the EBI.
30.4.1.12 Slower-Speed Clock Modes
For memories that cannot run with a full-speed external bus, the EBI supports slower-speed clock modes.
Refer to
Section 30.1.4.4, Slower-Speed Modes
for more details on this feature. The timing diagrams for
slower-speed modes are identical to those for full-speed mode, except that the frequency of D_CLKOUT
is reduced.
30.4.1.13 Stop and Module Disable Modes for Power Savings
Section 30.1.4, Modes of Operation
for a description of the power saving modes.
Table 30-12. Write/Byte Enable Signals Function
1
1
This table applies to aligned internal master transfers only. In the case of a misaligned internal master
transfer that is split into multiple aligned external transfers, not all of the write enables X’d in the table
will necessarily assert. See
Section 30.4.2.11, Misaligned Access Support
Transfer
Size
Address
32-Bit Port Size
16-Bit Port Size
2
2
Also applies when DBM=1 for 16-bit data bus mode.
A30
A31
D_WE
0
D_WE
1
D_WE
2
D_WE
3
D_WE
0
D_WE
1
D_WE
2
D_WE
3
Byte
0
0
X
X
0
1
X
X
1
0
X
X
1
1
X
X
16-bit
0
0
X
X
X
X
1
0
X
X
X
X
32-bit
0
0
X
X
X
X
X
3
3
This case consists of two 16-bit external transactions, but for both transactions the D_WE[0:1] signals
are the only D_WE signals affected.
Burst
0
0
X
X
X
X
X
X
Summary of Contents for PXR4030
Page 1: ...PXR40 Microcontroller Reference Manual Devices Supported PXR4030 PXR4040 PXR40RM Rev 1 06 2011...
Page 30: ...PXR40 Microcontroller Reference Manual Rev 1 Freescale Semiconductor xxx...
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Page 66: ...Memory Map PXR40 Microcontroller Reference Manual Rev 1 2 4 Freescale Semiconductor...
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