External Bus Interface (EBI)
30-22
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
30.4.2.2
Reset
Upon detection of internal reset assertion, the EBI immediately ends all transactions (abruptly, not through
normal termination protocol), and ignores any transaction requests that take place while reset is asserted.
30.4.2.3
Basic Transfer Protocol
The basic transfer protocol defines the sequence of actions that must occur on the external bus to perform
a complete bus transaction. A simplified scheme of the basic transfer protocol is shown in
.
Figure 30-8. Basic Transfer Protocol
The arbitration phase is where bus ownership is requested and granted. This phase is not needed in Single
Master Mode because the EBI is the permanent bus owner in this mode.
The address transfer phase specifies the address for the transaction and the transfer attributes that describe
the transaction. The signals related to the address transfer phase are D_TS, D_ADD (or D_ADD_DAT if
Address/Data multiplexing is used), CS[0:3], D_RD_WR, and D_BDIP. The address and its related signals
(with the exception of D_TS, D_BDIP) are driven on the bus with the assertion of the D_TS signal, and
kept valid until the bus master receives D_TA asserted (the EBI holds them one cycle beyond D_TA for
writes and external D_TA accesses). Note that for writes with internal D_TA, D_RD_WR is not held one
cycle past D_TA.
The data transfer phase performs the transfer of data, from master to slave (in write cycles) or from slave
to master (on read cycles), if any is to be transferred. The data phase may transfer a single beat of data (1-4
bytes) for non-burst operations or a 2-beat (special DBM=1 case only), 4-beat, 8-beat, or 16-beat burst of
data (2 or 4 bytes per beat depending on Port Size) when burst is enabled. On a write cycle, the master
must not drive write data until after the address transfer phase is complete. This is to avoid electrical
contentions when switching between drivers. The master must start driving write data one cycle after the
address transfer cycle. The master can stop driving the data bus as soon as it samples the D_TA line
asserted on the rising edge of D_CLKOUT. To facilitate asynchronous write support, the EBI keeps
driving valid write data on the data bus until 1 clock after the rising edge where D_RD_WR and WE are
negated (for chip-select accesses only). See
for an example of write timing. On a read cycle,
the master accepts the data bus contents as valid on the rising edge of the D_CLKOUT in which the D_TA
signal is sampled asserted. See
for an example of read timing.
The termination phase is where the cycle is terminated by the assertion of either D_TA (normal
termination) or D_TEA (termination with error). Termination is discussed in detail in
30.4.2.4
Single Beat Transfer
The flow and timing diagrams in this section assume that the EBI is configured in Single Master Mode.
Therefore, arbitration is not needed and is not shown in these diagrams.
Arbitration
Address Transfer
Data Transfer
Termination
Summary of Contents for PXR4030
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