External Bus Interface (EBI)
Freescale Semiconductor
30-27
PXR40 Microcontroller Reference Manual, Rev. 1
Figure 30-16. Single Beat 32-bit Write Cycle, Non-CS Access, Zero Wait States
30.4.2.4.3
Back-to-Back Accesses
Due to internal bus protocol, one dead cycle is necessary between back-to-back external bus accesses that
are not part of a set of small accesses (see
Section 30.4.2.6, Small Accesses (Small Port Size and Short
for small access timing). A dead cycle refers to a cycle between the D_TA of a previous
transfer and the D_TS of the next transfer.
NOTE
In some cases, CS remains asserted during this dead cycle, such as the cases
of back-to-back writes or read-after-write to the same chip-select. See
Besides this dead cycle, in most cases, back-to-back accesses on the external bus do not cause any change
in the timing from that shown in the previous diagrams, and the two transactions are independent of each
other. The only exceptions to this are listed below:
•
Back-to-back accesses where the first access ends with an externally-driven D_TA or D_TEA. In
these cases, an extra cycle is required between the end of the first access and the D_TS assertion
of the second access. See
Section 30.4.2.8, Termination Signals Protocol
for more details.
The following diagrams show a few examples of back-to-back accesses on the external bus.
D_ADD_DAT is valid
D_CLKOUT
D_ADD[9:30]
D_TS
D_TA (Input)
D_RD_WR
D_BDIP
CS[n]
D_ADD_DAT is valid
The EBI drives address and control signals an extra cycle because it uses a latched
version of the external D_TA (1 cycle delayed) to terminate the cycle.
*
*
D_ADD_DAT[0:31]
D_WE[0:3]
Summary of Contents for PXR4030
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