External Bus Interface (EBI)
30-42
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
If no device responds by asserting D_TA within the programmed timeout period (BMT in EBI_BMCR)
after the EBI initiates the bus cycle, the internal Bus Monitor (if enabled) asserts D_TEA to terminate the
cycle. An external device may also drive D_TEA when it detects an error on an external transaction.
D_TEA assertion causes the cycle to terminate and the processor to enter exception processing for the error
condition. To properly control termination of a bus cycle for a bus error with external circuitry, D_TEA
must be asserted at the same time or before (external) D_TA is asserted. D_TEA must be negated before
the second rising edge after it was sampled asserted in order to avoid the detection of an error for the
following bus cycle initiated. D_TEA is only driven by the EBI during the cycle where the EBI is asserting
D_TEA and the cycle immediately following this assertion (for fast negation). During all other cycles, the
EBI relies on a weak internal pullup to hold D_TEA negated. This allows an external device to assert
D_TEA when it needs to indicate an error. External devices must follow the same protocol as the EBI, only
driving D_TEA during the assertion cycle and 1 cycle afterwards for negation.
When D_TEA is asserted from an external source, the EBI uses a latched version of D_TEA (1 cycle
delayed) to help make timing at high frequencies. This means that for any accesses where the EBI drives
D_TA (chip-select accesses with SETA=0), a D_TEA assertion that occurs 1 cycle before or during the
last D_TA of the access could be ignored by the EBI, since it will have completed the access internally
before it detects the latched D_TEA assertion. This means that non-burst chip-select accesses with no wait
states (SCY=0) cannot be reliably terminated by external D_TEA. If external error termination is required
for such a device, the EBI must be configured for SCY>=1.
NOTE
For the cases discussed above where D_TEA “could be ignored”, this is not
gauranteed. For some small access cases (which always use chip-select and
internally-driven D_TA), a D_TEA that occurs 1 cycle before or during the
D_TA cycle or for SCY=0 may in fact lead to terminating the cycle with
error. However, proper error termination is not guaranteed for these cases,
so D_TEA must always be asserted at least 2 cycles before an
internally-driven D_TA cycle for proper error termination.
External D_TEA assertion that occurs during the same cycle that D_TS is asserted by the EBI is always
treated as an error (terminating the access) regardless of SCY.
summarizes how the EBI recognizes the termination signals provided from an external device.
shows an example of the termination signals protocol for back-to-back reads to two different
slave devices who properly “take turns” driving the termination signals. This assumes a system using slave
devices that drive termination signals.
Table 30-19. Termination Signals Protocol
D_TEA
1
1
Latched version (1 cycle delayed) used for externally
driven D_TEA and D_TA.
D_TA
Action
Negated
Negated
No Termination
Asserted
X
Transfer Error Termination
Negated
Asserted
Normal Transfer Termination
Summary of Contents for PXR4030
Page 1: ...PXR40 Microcontroller Reference Manual Devices Supported PXR4030 PXR4040 PXR40RM Rev 1 06 2011...
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