Resets
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor
4-11
4.7.2
Reset Configuration Timing
shows the relationship between reset signals and the configuration pins
for a power-on reset. The timing diagram is valid for internal and external resets assuming that VDD and
VDD33 are within valid operating ranges. The WKPCFG and PLLCFG signals are applied at the assertion
of the internal reset signal (assertion of RSTOUT). The values of the configuration pins are latched 4 clock
cycles before the negation of the RSTOUT pin and stored in the Reset Status Register and SYNSR register.
Figure 4-4. Reset Configuration Timing
4.7.3
Reset Weak Pull Up/Down Configuration
The signal on the WKPCFG pin determines whether specified eTPU and eMIOS pins are connected to
weak pull up or weak pull down devices at reset (see the Signal Description chapter for the eTPU and
eMIOS pins that are affected by WKPCFG). For all reset sources except the Software External Reset, the
WKPCFG pin is applied at the assertion of the internal reset signal (assertion of RSTOUT). If the
WKPCFG signal is logic high at this time, pull up devices will be enabled on the eTPU and eMIOS pins.
If the WKPCFG signal is logic low at the assertion of the internal reset signal, pull down devices will be
enabled on those pins. The value on WKPCFG must be held constant during reset to avoid oscillations on
RSTOUT
RESET
Internal
Reset
VDD
POR
PLL
xTAL Clock Ready
Crystal powering up or acquiring lock
WKPCFG,
BOOTCFG are
User drives
config pins relative
to RSTOUT
PLLREF is
(4 clock cycles)
PLL Locked
2400
1
clocks
‘Don’t Care’ and WKPCFG is
treated as ‘1’ during POR assertion.
PLLREF and WKPCFG
are applied, but not latched.
Note: 1. The clock count is dependent on the configuration of the PLL (refer to
). If the
PLL is configured in bypass mode, this clock count is 16000.
latched.
Pins start to
drive/sample when
POR negates
Summary of Contents for PXR4030
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