Nexus Development Interface (NDI)
31-26
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
31.7.2.4
Nexus Auxiliary Port Sharing
Each of the Nexus modules on the MCU implements a request/grant scheme to arbitrate for control of the
Nexus auxiliary port when Nexus data is ready to be transmitted.
All modules arbitrating for the port are given fixed priority levels relative to each other. If multiple
modules have the same request level, this priority level is used as a tie-breaker. To avoid monopolization
of the port, the module given the highest priority level alternates following each grant. Immediately out of
reset the order of priority, from highest to lowest, is: NPC, NZ7C3, NDEDI, NXDM and NXFR. This
arbitration mechanism is controlled internally and is not programmable by tools or the user.
31.7.2.5
Nexus JTAG Port Sharing
Each of the individual Nexus modules on the device implements a TAP controller for accessing its
registers. When JCOMP is asserted, only the module whose ACCESS_AUX_TAP instruction is loaded
has control of the TAP (see
Section 32.4.4, JTAGC Instructions
). This allows the interface to all of these
individual TAP controllers to appear to be a single port from outside the device. After a Nexus module has
ownership of the TAP, that module acts like a single-bit shift register, or bypass register, if no register is
selected as the shift path.
31.7.2.6
MCKO
MCKO is an output clock to the development tools used for the timing of MSEO and MDO pin functions.
MCKO is derived from the system clock and its frequency is determined by the value of the
MCKO_DIV[2:0] field in the PCR. Possible operating frequencies include one-half, one-quarter, and
one-eighth system clock speed. MCKO is enabled by setting the MCKO_EN bit in the PCR.
The NPC also controls dynamic MCKO clock gating when in full- or reduced-port modes. The setting of
the MCKO_GT bit inside the PCR determines whether or not MCKO gating control is enabled. The
MCKO_GT bit resets to a logic 0. In this state gating of MCKO is disabled. To enable gating of MCKO,
the MCKO_GT bit in the PCR is written to a logic 1. When MCKO gating is enabled, MCKO is driven to
a logic 0 if the auxiliary port is enabled but not transmitting messages and there are no pending messages
from Nexus clients.
31.7.2.7
EVTO Sharing
The NPC controls sharing of the EVTO output between all Nexus clients that produce an EVTO signal.
EVTO is driven for one MCKO period whenever any module drives its EVTO. When there is no active
MCKO, such as in disabled mode, the NPC assumes an MCKO frequency of one-half system clock speed
when driving EVTO. EVTO sharing is active as long as the NPC is not in reset.
48
1
UPDATE-DR
DATA_ACCESS
Value written to register
49
0
RUN-TEST/IDLE
REG_SELECT
Controller returned to idle state. It could also return
to SELECT-DR-SCAN to write another register.
Table 31-15. Write to a 32-Bit Nexus Client Register (continued)
Clock
TMS
IEEE 1149.1 State
Nexus State
Description
Summary of Contents for PXR4030
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