Nexus Development Interface (NDI)
Freescale Semiconductor
31-59
PXR40 Microcontroller Reference Manual, Rev. 1
3. The NZ7C3 module then arbitrates for the system bus and the read data is transferred from the
system bus to the RWD register. When the transfer is completed without error (ERR = 0), Nexus
asserts the RDY pin and sets the DV bit in the RWCS register. This indicates that the device is
ready for the next access.
4. The data can then be read from the read/write access data register (RWD) through the access
Section 31.11.1, NZ7C3 Register Access via JTAG / OnCE
, using the Nexus
).
NOTE
Only the RDY pin as well as the DV and ERR bits within the RWCS provide
Read/Write Access status to the external development tool.
31.14.8.5 Block Read Access (Non-Burst Mode)
1. For a non-burst block read access, follow Steps 1 and 2 outlined in
Section 31.14.8.4, Single Read
, to initialize the registers, but using a value greater than one (0x1) for the CNT field in the
RWCS register.
2. The NZ7C3 module then arbitrates for the system bus and the read data is transferred from the
system bus to the RWD register. When the transfer has completed without error (ERR=0b0), the
address from the RWA register is incremented to the next word size (specified in the SZ field) and
the number from the CNT field is decremented. Nexus then asserts the RDY pin. This indicates
that the device is ready for the next access.
3. The data can then be read from the read/write access data register (RWD) through the access
Section 31.11.1, NZ7C3 Register Access via JTAG / OnCE
, using the Nexus
).
4. Repeat steps 3 and 4 in
Section 31.14.8.4, Single Read Access
, until the CNT value is zero (0).
When this occurs, the DV bit within the RWCS is set to indicate the end of the block read access.
31.14.8.6 Block Read Access (Burst Mode)
1. For a burst block read access, follow Steps 1 and 2 outlined in
Section 31.14.8.4, Single Read
, to initialize the registers, using a value of four (doublewords) for the CNT field and an
RWCS[SZ] field indicating 64-bit access.
2. The NZ7C3 module then arbitrates for the system bus and the burst read data is transferred from
the system bus to the data buffer (RWD register). For each access within the burst, the address from
the RWA register is incremented to the next doubleword (specified in the SZ field) and the number
from the CNT field is decremented.
3. When the entire burst transfer has completed without error (ERR = 0), Nexus then asserts the RDY
pin and the DV bit within the RWCS is set to indicate the end of the block read access.
4. The data can then be read from the burst data buffer (read/write access data register) through the
access method outlined in
Section 31.11.1, NZ7C3 Register Access via JTAG / OnCE
Nexus register index of 0xA (see
5. Repeat step 3 until all doubleword values are read from the buffer.
Summary of Contents for PXR4030
Page 1: ...PXR40 Microcontroller Reference Manual Devices Supported PXR4030 PXR4040 PXR40RM Rev 1 06 2011...
Page 30: ...PXR40 Microcontroller Reference Manual Rev 1 Freescale Semiconductor xxx...
Page 40: ...PXR40 Microcontroller Reference Manual Rev 1 xl Freescale Semiconductor...
Page 66: ...Memory Map PXR40 Microcontroller Reference Manual Rev 1 2 4 Freescale Semiconductor...
Page 120: ...Signal Descriptions 3 54 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...
Page 860: ...FlexCAN Module 24 50 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...
Page 1167: ...Decimation Filter Freescale Semiconductor 28 53 PXR40 Microcontroller Reference Manual Rev 1...
Page 1168: ...Decimation Filter 28 54 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...
