Device Performance Optimization
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor
33-5
array. Code for configuring the Flash should be executed from a separate memory array i.e copied to and
executed from system RAM.
Section 12.2.2.8, Flash Bus Interface Configuration Register (FLASH_BIUCR)
, contains the required
Flash wait state settings for a given operating frequency. This also provides recommendations for the
prefetch buffer settings. Note that the BIUCRx settings may vary between revisions of the PXR40.
33.3.4
Crossbar Switch
33.3.4.1
Description
The multi-port crossbar switch (XBAR) supports simultaneous connections between master ports and
slave ports. The XBAR allows for concurrent transactions to occur from any master port to any slave port.
If a slave port is simultaneously requested by more than one master port, arbitration logic selects the higher
priority master and grants it ownership of the slave port. All other masters requesting that slave port are
stalled until the higher priority master completes its transactions. By default, requesting masters are
granted access based on a fixed priority. A round-robin priority mode also is available.
The main goal of the XBAR is to increase overall system performance by allowing multiple masters to
communicate concurrently with multiple slaves. In order to maximize data throughput it is essential to
keep arbitration delays to a minimum. The configuration of the crossbar can have implications for the
performance of a system and particular care should be taken when assigning master priorities in a fixed
priority application. Further, by correctly parking saves on relevant masters the initial access times to the
slaves can be minimized by negating any initial arbitration penalties.
33.3.4.2
Recommended Configuration
The specific settings for a given situation are application dependent and thus should be assessed by the
user. however, some general guidelines are available.
Optimal XBAR settings are application dependent, but in e200z4/7 (Harvard configuration) based devices
assigning the CPU data bus to have highest priority and parking the slave port associated with system
RAM on this master generally provides the best overall performance.
To reconfigure the XBAR as described on the PXR40, write the following resisters:
1. XBAR_SGPCR2 = 0x0000_0001. This parks the slave 2 (internal SRAM) on master port 1 (CPU
data bus)
2. Write XBAR_MPR0 = 0x5432_0001. This sets slave port 0 (Flash) to give the master port 1 (CPU
data bus) highest priority.
On the e200z4/z7 based devices it may also be beneficial to assign the eDMA to have highest priority for
the Flash slave port depending upon the application.
More details of the XBAR register configuration can be found in
Summary of Contents for PXR4030
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