Device Performance Optimization
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor
33-9
Note that configuration of the cache has to be performed in conjunction with configuration of the Memory
Management unit. Refer to section
Section 33.3.6, Memory Management Unit (MMU)
33.3.6
Memory Management Unit (MMU)
33.3.6.1
Description
The Memory Management Unit is a 32-bit
PowerPC Book E
compliant implementation which provides
functionality that includes address translation and application of access attributes to memory ranges
defined in Translation Lookaside Buffer entries. Although the MMU does not directly impact
performance, it is within the MMU that memory regions are configured to permit the use of system cache
to improve performance and Variable Length Encoding (VLE) to enhance code density. Thus it is essential
that the MMU is correctly configured to ensure optimal application performance is achieved.
33.3.6.1.1
Recommended configuration
The core uses MMU Assist Registers (MASx) which are special purpose registers to facilitate reading,
writing & searching the Translation Lookaside Buffer (TLB) entries. These MAS registers are software
29
DCABT
Data Cache Operation Aborted
Indicates a Cache Invalidate or a Cache Lock Bits Flash Clear operation was aborted prior to completion.
This bit is set by hardware on an aborted condition, and will remain set until cleared by software writing
0 to this bit location.
30
DCINV
Data Cache Invalidate
0 - No cache invalidate
1 - Cache invalidation operation
When written to a ‘1’, a cache invalidation operation is initiated by hardware. Once complete, this bit is
reset to ‘0’. Writing a ‘1’ while an invalidation operation is in progress will result in an undefined opera-
tion. Writing a ‘0’ to this bit while an invalidation operation is in progress will be ignored. Cache invalida-
tion operations require approximately 134 cycles to complete. Invalidation occurs regardless of the
enable (DCE) value.
During cache invalidations, the parity check bits are written with a value dependent on the DCEDT
selection. DCEDT should be written with the desired value for subsequent cache operation when DCINV
is set to ‘1’ for proper operation of the cache.
31
DCE
Data Cache Enable
0 - Cache is disabled
1 - Cache is enabled
When disabled, cache lookups are not performed for normal load or store accesses, or for snoop
requests.
Other L1CSR0 cache control operations are still available. Also, operation of the store buffer is not
affected by DCE.
Table 33-3. L1CSR0 Register Field Descriptions (continued)
Field
Description
Summary of Contents for PXR4030
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