Frequency Modulated Phase-Locked Loop (FMPLL)
Freescale Semiconductor
6-15
PXR40 Microcontroller Reference Manual, Rev. 1
frequency modulation enabled. The post-divider is capable of reducing the PLL clock frequency without
forcing a re-lock. The PLL reference can be a crystal oscillator reference or an external clock reference.
This clock is divided by the pre-divider circuit to create the PLL reference clock.
6.4.3.1
PLL Lock Detection
The lock detect logic monitors the reference frequency and the PLL feedback frequency to determine when
frequency lock has been achieved. Phase lock is inferred by the frequency relationship, but is not
guaranteed. The PLL lock status is reflected in the LOCK status bit in the SYNSR. A sticky lock status
indication, LOCKS, is also provided.
The lock detect function uses two counters, which are clocked by the reference and PLL feedback
respectively. When the reference counter has counted N cycles, the feedback counter’s count is compared.
If the feedback counter has also counted N cycles, the process is repeated for N + K counts. Then if the
two counters’ counts match, the lock criteria is relaxed by one count and the system is notified that the
PLL has achieved frequency lock. After three successful compares, the tolerance is relaxed.
After lock has been detected, the lock circuitry continues to monitor the reference and feedback
frequencies using the alternate count and compare process. If the counters do not match at any comparison
time, then the LOCK status bit is cleared to indicate that the PLL has lost lock. At this point, the lock
criteria is tightened and the lock detect process is repeated.
The alternate count sequences prevent false lock detects due to frequency aliasing while the PLL tries to
lock. Alternating between a tight and relaxed lock criteria prevents the lock detect function from randomly
toggling between locked and not locked status due to phase sensitivities.
illustrates the
sequence for detecting locked and not-locked conditions.
When the frequency modulation is enabled, the loss of lock continues to function as described but with the
lock and loss of lock criteria reduced to ensure that false loss of lock conditions are not detected.
In PLL Off mode, the PLL cannot lock because the PLL is disabled.
Summary of Contents for PXR4030
Page 1: ...PXR40 Microcontroller Reference Manual Devices Supported PXR4030 PXR4040 PXR40RM Rev 1 06 2011...
Page 30: ...PXR40 Microcontroller Reference Manual Rev 1 Freescale Semiconductor xxx...
Page 40: ...PXR40 Microcontroller Reference Manual Rev 1 xl Freescale Semiconductor...
Page 66: ...Memory Map PXR40 Microcontroller Reference Manual Rev 1 2 4 Freescale Semiconductor...
Page 120: ...Signal Descriptions 3 54 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...
Page 860: ...FlexCAN Module 24 50 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...
Page 1167: ...Decimation Filter Freescale Semiconductor 28 53 PXR40 Microcontroller Reference Manual Rev 1...
Page 1168: ...Decimation Filter 28 54 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...
