Frequency Modulated Phase-Locked Loop (FMPLL)
6-20
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
Figure 6-8. Frequency Modulation Waveform
6.4.3.4.1
Frequency Modulation Control
The frequency modulation control consists of programming a reference current into the modulation D/A
so that the modulation depth (F
max
and F
min
) remains within specification. Disable frequency modulation
prior to changing the EPREDIV, EMFD, or ERATE bit fields. Upon enabling frequency modulation a new
configuration sequence is required. Do not change EPREDIV, EMFD or ERATE while modulation is
active or unpredictable results may occur.
6.4.3.4.2
Programming System Clock Frequency With Frequency Modulation
The following steps illustrate proper programming of the frequency modulation mode. These steps ensure
proper operation of the FM configuration routine and prevent frequency overshoot from the programming
sequence. The PLL should be programmed and allowed to lock in non-FM mode at the desired frequency
as outlined in
Section 6.4.3.3.5, Programming System Clock Frequency
.
1. Write a value of ERFD = ERFD + 2 to the ERFD field of the ESYNCR2 to ensure the maximum
system frequency is not exceeded during the FM configuration. This is done when allowing the
PLL to lock in non-FM mode.
NOTE
Even numbered ERFD settings, which would result in odd divide ratios, are
invalid and cause the PLL to produce an unpredictable output clock. The
PLL output clock must be within the f
PLL
specification
F
max
F
min
t
1
F
mod
----------------
=
t
f
F
max
= F
sys
+ {0.5%, 1%, 1.5%, 2%}
F
min
= F
sys
– {0.5%, 1%,1.5%, 2%}
F
mod
= F
extal
/Q where Q = {20, 40, 80}
Fm
Fm
Summary of Contents for PXR4030
Page 1: ...PXR40 Microcontroller Reference Manual Devices Supported PXR4030 PXR4040 PXR40RM Rev 1 06 2011...
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