System Integration Unit (SIU)
Freescale Semiconductor
7-75
PXR40 Microcontroller Reference Manual, Rev. 1
7.3.1.32
Masked Parallel GPIO Pin Data Output Register (SIU_MPGPDO0 -
SIU_MPGPDO31)
The MPGPDOx registers are written to by software to drive data out on the external GPIO pin (they are
write-only registers and reading them will return 0; reading must be done by accessing the corresponding
SIU_GPDO register). These registers access the same GPIO pins accessed by SIU_GPDO0–
SIU_GPDO511 bit registers. The most significant 16 bits in the SIU_MPGPDO registers should map
directly to these registers. For example, SIU_MPGPDO0 bit 31 is SIU_GPDO15 bit 7, SIU_MPGPDO0
bit 30 is SIU_GPDO17 bit 7,...., SIU_MPGPD15 bit 16 is SIU_GPDO240 bit 7. The least significant
sixteen bits are the corresponding values to be written at GPIO pins defined by MASK field. The masked
parallel GPIO read/write should be decode the logical addresses to the same physical address of the normal
GPIO.
Figure 7-30. Masked Parallel GPIO Pin Data Output Register (SIU_MPGPDO0 - SIU_MPGPDO31)
Table 7-50. SIU_PGPDI0 - SIU_PGPDI15 - SIU_PGPDO15 Field Descriptions
Field
Description
0–31
PGPDIx
Pin Data In. Stores the value of the pad-interface signals (data in) corresponding to the external GPIO pin
associated with the register.
0 The value of the pad-interface signals (data in) for the corresponding GPIO pin is logic low.
1 The value of the pad-interface signals (data in) for the corresponding GPIO pin is logic high.
SI 0xC80 - SI 0xCFC (32)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
W
MASK
0
MASK
1
MASK
2
MASK
3
MASK
4
MASK
5
MASK
6
MASK
7
MASK
8
MASK
9
MASK
10
MASK
11
MASK
12
MASK
13
MASK
14
MASK
15
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
W
DATA
0
DATA
1
DATA
2
DATA
3
DATA
4
DATA
5
DATA
6
DATA
7
DATA
8
DATA
9
DATA
10
DATA
11
DATA
12
DATA
13
DATA
14
DATA
15
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 7-51. SIU_MPGPDO0 - SIU_MPGPDO31 Field Descriptions
Field
Description
0–15
MASKx
Pin Data Out. Controls the write access to the corresponding GPDO.
0 Previous value defined by GPDO is maintain.
1 Corresponding GPDO is written with value defined by DATA field.
16–31
DATAx
Pin Data Out. Stores the data to be driven out on the external GPIO pin controlled by this register.
0 Logic low value is driven on the pad interface data out signal for the corresponding GPIO pin when the
pin is configured as an output.
1 Logic high value is driven on the pad interface data out signal for the corresponding GPIO pin when the
pin is configured as an output.
Summary of Contents for PXR4030
Page 1: ...PXR40 Microcontroller Reference Manual Devices Supported PXR4030 PXR4040 PXR40RM Rev 1 06 2011...
Page 30: ...PXR40 Microcontroller Reference Manual Rev 1 Freescale Semiconductor xxx...
Page 40: ...PXR40 Microcontroller Reference Manual Rev 1 xl Freescale Semiconductor...
Page 66: ...Memory Map PXR40 Microcontroller Reference Manual Rev 1 2 4 Freescale Semiconductor...
Page 120: ...Signal Descriptions 3 54 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...
Page 860: ...FlexCAN Module 24 50 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...
Page 1167: ...Decimation Filter Freescale Semiconductor 28 53 PXR40 Microcontroller Reference Manual Rev 1...
Page 1168: ...Decimation Filter 28 54 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...
