System Integration Unit (SIU)
Freescale Semiconductor
7-79
PXR40 Microcontroller Reference Manual, Rev. 1
Figure 7-31. Masked Serial GPO Register for DSPI - DSPI_A/B/C/D GPO Mask Output High Register
(SIU_DSPIAH/SIU_DSPIBH/SIU_DSPICH/SIU_DSPIDH)
Figure 7-32. Masked Serial GPO Register for DSPI - DSPI_A/B/C/D GPO Mask Output Low Register
(SIU_DSPIAL/SIU_DSPIBL/SIU_DSPICL/SIU_DSPIDL)
7.3.1.33.2
Serialized Output Signal Selection Registers for DSPI_A
The following three registers are used by DSPI_A to select the sources of the serialized output when
running in DSI or CSI configuration.
Each register bit enables a path from the eTPU_B channel, eMIOS channel and data register bit
SIU_DSPIAH/SIU_DSPIAL to the equivalent bit position in the DSPI_A serialized output frame. The
user must ensure that bit selections from each of these registers do not overlap. Multiple sources are
SI 0xD00, SI 0xD08, SI 0xD10, SI 0xD18
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
W
MASK
0
MASK
1
MASK
2
MASK
3
MASK
4
MASK
5
MASK
6
MASK
7
MASK
8
MASK
9
MASK
10
MASK
11
MASK
12
MASK
13
MASK
14
MASK
15
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
DATA
0
DATA
1
DATA
2
DATA
3
DATA
4
DATA
5
DATA
6
DATA
7
DATA
8
DATA
9
DATA
10
DATA
11
DATA
12
DATA
13
DATA
14
DATA
15
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SI 0xD04, SI 0xD0C, SI 0xD14, SI 0xD1C
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
W
MASK
16
MASK
17
MASK
18
MASK
19
MASK
20
MASK
21
MASK
22
MASK
23
MASK
24
MASK
25
MASK
26
MASK
27
MASK
28
MASK
29
MASK
30
MASK
31
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
DATA
16
DATA
17
DATA
18
DATA
19
DATA
20
DATA
21
DATA
22
DATA
23
DATA
24
DATA
25
DATA
26
DATA
27
DATA
28
DATA
29
DATA
30
DATA
31
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 7-53. SIU_DSPIAL/SIU_DSPIBL/SIU_DSPICL/SIU_DSPIDL Field Descriptions
Field
Description
0–15
MASKx
Pin Data Out. Controls the write access to the corresponding GPO for DSPI. These bits are write-only and
read as 0.
0 Previous value defined by GPDO is maintained.
1 Corresponding GPO is written with value defined by DATA field.
Note: The MASK bits have to be written at the same time (same access cycle) as the DATA bits, for the mask
to work (the MASK information is not stored).
16–31
DATAx
Pin Data Out. Stores the data to be driven out on the external GPIO pin controlled by this register.
0 Logic low value is driven on the pad interface data out signal for the corresponding GPO for DSPI when
this output is selected in the DSPI serialization module.
1 Logic high value is driven on the pad interface data out signal for the corresponding GPO for DSPI when
this output is selected in the DSPI serialization module.
Summary of Contents for PXR4030
Page 1: ...PXR40 Microcontroller Reference Manual Devices Supported PXR4030 PXR4040 PXR40RM Rev 1 06 2011...
Page 30: ...PXR40 Microcontroller Reference Manual Rev 1 Freescale Semiconductor xxx...
Page 40: ...PXR40 Microcontroller Reference Manual Rev 1 xl Freescale Semiconductor...
Page 66: ...Memory Map PXR40 Microcontroller Reference Manual Rev 1 2 4 Freescale Semiconductor...
Page 120: ...Signal Descriptions 3 54 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...
Page 860: ...FlexCAN Module 24 50 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...
Page 1167: ...Decimation Filter Freescale Semiconductor 28 53 PXR40 Microcontroller Reference Manual Rev 1...
Page 1168: ...Decimation Filter 28 54 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...
