Interrupts and Interrupt Controller (INTC)
Freescale Semiconductor
10-5
PXR40 Microcontroller Reference Manual, Rev. 1
— ISR at a higher priority preempts ISRs or tasks at lower priorities.
— Automatic pushing or popping of preempted priority to or from a LIFO.
— Ability to modify the ISR or task priority. Modifying the priority can be used to implement the
priority ceiling protocol for accessing shared resources.
•
Low latency–three clocks from receipt of interrupt request from peripheral to interrupt request to
processor.
10.1.4
Modes of Operation
The interrupt controller has two handshaking modes with the processor: software vector mode and
hardware vector mode. The state of the hardware vector enable bit, INTC_MCR[HVEN], determines
which mode is used.
In debug mode the interrupt controller operation is identical to its normal operation of software vector
mode or hardware vector mode.
10.1.4.1
Software Vector Mode
In software vector mode, there is a common interrupt exception handler address which is calculated by
hardware as shown in
. The upper half of the interrupt vector prefix register (IVPR) is added
to the offset contained in the external input interrupt vector offset register (IVOR4). Note that since bits
IVOR4[28:31] are not part of the offset value, the vector offset must be located on a quad-word (16-byte)
aligned location in memory.
In software vector mode, the interrupt exception handler software must read the INTC interrupt
acknowledge register (INTC_IACKR) to obtain the vector number and base address of the handler
associated with the corresponding peripheral or software interrupt request. The INTC_IACKR register
contains a 21-bit or 20-bit address for a vector table base address (VTBA). The address is then used to
branch to the corresponding routine for that peripheral or software interrupt source.
Figure 10-5. Software Vector Mode: Interrupt Exception Handler Address Calculation
Reading the INTC_IACKR acknowledges the INTC’s interrupt request and negates the interrupt request
to the processor. The interrupt request to the processor does not clear if a higher priority interrupt request
arrives. Even in this case, INTVEC does not update to the higher priority request until the lower priority
31
16
15
0
IVPR
31
28
27
16
15
0
+ IVOR4
31
28
27
16
15
0
0x00
0x00
OFFSET
OFFSET
PREFIX
0x0000
PREFIX
= Interrupt exception
0x0000
handler address
Summary of Contents for PXR4030
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