Flash Memory Array and Control
12-12
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
If the user attempts to write two or more FLASH_x_MCR bits simultaneously then only the bit with the
lowest priority level is written. Setting two bits with the same priority level is prevented by existing write
locks or do not put the flash in an illegal state.
For example, setting ERS and PGM simultaneously results in only ERS being set. Attempting to clear
EHV while setting PSUS results in EHV being cleared, while PSUS is unaffected.
12.2.2.2
Low/Mid Address Space Block Locking Register (FLASH_x_LMLR)
The Low/Mid Address Block Locking Register (FLASH_x_LMLR) provides a means to protect blocks
from being modified. These bits, along with bits in the Secondary LLOCK (FLASH_
x
_SLMLR),
determine if the block is locked from program or erase. An “OR” of FLASH_
x
_LMLR and
FLASH_x_SLMLR determine the final lock status.
NOTE
A reset value of 1* in
indicates that the reset value of these
registers is determined by Flash values in the shadow block. An erased
shadow block causes the reset value to be 1.
The following field and bit descriptions fully define the FLASH_x_LMLR register (
FLASH_x_LMLR register functions, as shown in
.
Table 12-5. FLASH_x_MCR Bit Set/Clear Priority Levels
Priority Level
FLASH_x_MCR Bit(s)
1
ERS
2
PGM
3
EHV
4
ESUS, PSUS
Offset 0x0004 / 0x4004
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12 13
14
15
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
LME
0
0
0 0
0
0 0 0
0
0
SLOCK
0
0
MLOCK
0
0
0
0
0
0
LLOCK
W
Reset
0
0
0
0 0
0
0 0 0
0
0
1*
0
0
1*
1*
0
0
0
0
0
0 1* 1* 1* 1* 1* 1* 1* 1* 1* 1*
Figure 12-4. FLASH_x_LMLR Register
Summary of Contents for PXR4030
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