Memory Protection Unit (MPU)
Freescale Semiconductor
16-11
PXR40 Microcontroller Reference Manual, Rev. 1
Table 16-8. MPU_RGD Word 2 Description
Field
Description
Note: For future code compatibility, do not change the value of reserved bits from their reset value
0–1
Reserved
2
4
6
MnRE
Bus Master ID n Read Enable. If set, this flag allows bus master ID n to perform read operations. If cleared, any
attempted read by bus master ID n terminates with an access error and the read is not performed.
Note: See
for the MPU Master ID list.
3
5
7
MnWE
Bus Master ID n Write Enable. If set, this flag allows bus master ID n to perform write operations. If cleared, any
attempted write by bus master ID n terminates with an access error and the write is not performed.
Note: See
for the MPU Master ID list.
8–25
Reserved
26
M0PE
Bus Master ID 0 Process Identifier Enable. If set, this flag specifies that the process identifier and mask defined in
MPU_RGDn.Word3 are to be included in the region hit evaluation. If cleared, the region hit evaluation does not
include the process identifier.
Note: See
for the MPU Master ID list.
27–28
M0SM
Bus Master ID 0 Supervisor Mode Access Control. This 2-bit field defines the access controls for bus master ID 0
when operating in supervisor mode. The M0SM field is defined as:
00
r, w, x =
read, write and execute allowed
01
r, –, x =
read and execute allowed, but no write
10
r, w, – =
read and write allowed, but no execute
11 Same access controls as that defined by M0UM for user mode
Note: See
for the MPU Master ID list.
29–31
M0UM
Bus Master ID 0 User Mode Access Control. This 3-bit field defines the access controls for bus master ID 0 when
operating in user mode. The M0UM field consists of three independent bits, enabling read, write, and execute
permissions:
{r,w,x}
. If set, the bit allows the given access type to occur; if cleared, an attempted access of that
mode may be terminated with an access error (if not allowed by any other descriptor) and the access not performed.
Note: See
for the MPU Master ID list.
Summary of Contents for PXR4030
Page 1: ...PXR40 Microcontroller Reference Manual Devices Supported PXR4030 PXR4040 PXR40RM Rev 1 06 2011...
Page 30: ...PXR40 Microcontroller Reference Manual Rev 1 Freescale Semiconductor xxx...
Page 40: ...PXR40 Microcontroller Reference Manual Rev 1 xl Freescale Semiconductor...
Page 66: ...Memory Map PXR40 Microcontroller Reference Manual Rev 1 2 4 Freescale Semiconductor...
Page 120: ...Signal Descriptions 3 54 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...
Page 860: ...FlexCAN Module 24 50 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...
Page 1167: ...Decimation Filter Freescale Semiconductor 28 53 PXR40 Microcontroller Reference Manual Rev 1...
Page 1168: ...Decimation Filter 28 54 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...
