Memory Protection Unit (MPU)
16-12
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
16.2.2.4.4
MPU Region Descriptor n, Word 3 (MPU_RGDn.Word3)
The fourth word of the MPU region descriptor contains the optional process identifier and mask, plus the
region descriptor’s valid bit.
Because the region descriptor is a 128-bit entity, there are potential coherency issues as this structure is
being updated because multiple writes are required to update the entire descriptor. Accordingly, the MPU
hardware assists in the operation of the descriptor valid bit to prevent incoherent region descriptors from
generating spurious access errors. In particular, it is expected that a complete update of a region descriptor
is typically done with sequential writes to MPU_RGD
n
.Word0, then MPU_RGD
n
.Word1, ... and
MPU_RGD
n
.Word3. The MPU hardware automatically clears the valid bit on any writes to words {0,1,2}
of the descriptor. Writes to this word set/clear the valid bit in a normal manner.
Because it is also expected that system software may adjust the access controls within a region descriptor
(MPU_RGDn.Word2) only as different tasks execute, an alternate programming view of this 32-bit entity
is provided. If only the access controls are being updated, this operation must be performed by writing to
MPU_RGDAAC
n
(alternate access control
n
) as stores to these locations do not affect the descriptor’s
valid bit.
Offset: MP 0x400 + (16*n) + 0xc (MPU_RGDn.Word3)
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
PID
PIDMASK
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
V
L
D
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 16-8. MPU Region Descriptor, Word 3 Register (MPU_RGDn.Word3)
Table 16-9. MPU_RGD Word 3 Description
Field
Description
0–7
PID
Process Identifier. This 8-bit field specifies that the optional process identifier is to be included in the determination
of whether the current access hits in the region descriptor. This field is combined with the PIDMASK and included
in the region hit determination if MPU_RGDn.Word2[MxPE] is set.
8–15
PIDMASK
Process Identifier Mask. This 8-bit field provides a masking capability so that multiple process identifiers can be
included as part of the region hit determination. If a bit in the PIDMASK is set, the corresponding bit of the PID is
ignored in the comparison. This field is combined with the PID and included in the region hit determination if
MPU_RGDn.Word2[MxPE] is set. For more information on the handling of the PID and PIDMASK, see
Section 16.3.1.1, Access Evaluation—Hit Determination
.
16–30
Reserved
31
VLD
Valid. This bit signals the region descriptor is valid. Any write to MPU_RGDn.Word{0,1,2} clears this bit, but a write
to MPU_RGDn.Word3 sets or clears this bit depending on bit 31 of the write operand.
0 Region descriptor is invalid
1 Region descriptor is valid
Summary of Contents for PXR4030
Page 1: ...PXR40 Microcontroller Reference Manual Devices Supported PXR4030 PXR4040 PXR40RM Rev 1 06 2011...
Page 30: ...PXR40 Microcontroller Reference Manual Rev 1 Freescale Semiconductor xxx...
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