Memory Protection Unit (MPU)
16-14
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
16.3
Functional Description
In this section, the functional operation of the MPU is detailed. In particular, subsequent sections discuss
the operation of the access evaluation macro as well as the handling of error-terminated AHB bus cycles.
16.3.1
Access Evaluation
As discussed, the basic operation of the MPU is performed in the access evaluation macro, a hardware
structure replicated in the two-dimensional connection matrix. The access evaluation macro inputs the
AHB system bus address and the contents of a region descriptor (RGD
n
) and performs two major
functions: region hit determination and detection of an access protection violation.
16.3.1.1
Access Evaluation—Hit Determination
To determine if the current AHB reference hits in the given region, two magnitude comparators are used
with the region’s start and end addresses. There are no hardware checks to verify that the region end
address is greater than or equal to the region start address. The software must properly load appropriate
values into these fields of the region descriptor.
In addition to the comparison of the AHB reference address versus the region descriptor’s start and end
addresses, the optional process identifier is examined against the region descriptor’s PID and PIDMASK
fields. For AHB bus masters that do not output a process identifier, the MPU forces the PID term to be
asserted.
16.3.1.2
Access Evaluation—Privilege Violation Determination
While the access evaluation macro is making the region hit determination, the logic is also evaluating if
the current access is allowed by the permissions defined in the region descriptor. Using the AHB
supervisor/user mode signals, a set of permissions is generated from the appropriate fields in the region
descriptor. The protection violation logic evaluates the access against the effective permissions.
26
M0PE
Bus Master 0 Process Identifier Enable. If set, this flag specifies that the process identifier and mask (defined in
MPU_RGDn.Word3) are to be included in the region hit evaluation. If cleared, then the region hit evaluation does
not include the process identifier.
27–28
M0SM
Bus Master 0 Supervisor Mode Access Control. This 2-bit field defines the access controls for bus master 0 when
operating in supervisor mode. The M0SM field is defined as:
00
r, w, x =
read, write and execute allowed
01
r, –, x =
read and execute allowed, but no write
10
r, w, – =
read and write allowed, but no execute
11 Same access controls as that defined by M0UM for user mode
Note: See
for the MPU Master ID list.
29–31
M0UM
Bus Master 0 User Mode Access Control. This 3-bit field defines the access controls for bus master 0 when
operating in user mode. The M0UM field consists of three independent bits, enabling read, write, and execute
permissions:
{r,w,x}
. If set, the bit allows the given access type to occur; if cleared, an attempted access of that
mode may be terminated with an access error (if not allowed by any other descriptor) and the access not performed.
Note: See
for the MPU Master ID list.
Table 16-10. MPU_RGDAAC Bit Field Descriptions (continued)
Field
Description
Summary of Contents for PXR4030
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