Memory Protection Unit (MPU)
Freescale Semiconductor
16-15
PXR40 Microcontroller Reference Manual, Rev. 1
The access evaluation macro then uses the hit and permission signals to determine if the current access is
allowed and the MPU_EDR
n
(error detail register) is updated in the event of an error.
16.3.2
AHB Error Terminations
For each AHB slave port being monitored, the MPU tests any access for permission violations as above.
If a violation occurs, the MPU terminates the bus cycle and reports a protection error for three conditions:
1. If the access does not hit in any region descriptor, a protection error is reported.
2. If the access hits in a single region descriptor and that region signals a protection violation, a
protection error is reported.
3. If the access hits in multiple (overlapping) regions and all regions signal protection violations, then
a protection error is reported.
The third condition reflects that priority is given to permission granting over access denying for
overlapping regions as this approach provides more flexibility to system software in region descriptor
assignments. For an example of the use of overlapping region descriptors, see
When the MPU causes a termination error to occur, the effect on the system depends on the bus master
requesting the access. If the error was caused by a core access, a machine check is taken. If the error was
caused by an eDMA access, an eDMA source or destination error occurs in the eDMA controller, which
can be enabled to provide an interrupt request through the INTC. If the error was caused by a FlexRay
access, a controller host interface (CHI) illegal system memory access error occurs in the FlexRay
controller, which can be enabled to provide an interrupt request to the INTC.
16.4
Initialization Information
The reset state of MPU_CESR[VLD] disables the entire module. While the MPU is disabled, all accesses
from all bus masters are allowed. This state also minimizes the power dissipation of the MPU. The power
dissipation of each access evaluation macro is minimized when the associated region descriptor is marked
as invalid or when MPU_CESR[VLD] = 0.
Typically the appropriate number of region descriptors (MPU_RGD
n
) are loaded at system startup,
including the setting of the MPU_RGD
n
.Word3[VLD] bits, before MPU_CESR[VLD] is set, enabling the
module. This approach allows all the loaded region descriptors to be enabled simultaneously. Once the
MPU is enabled, if a memory reference does not hit in any region descriptor, the attempted access is
terminated with an error.
16.5
Application Information
In an application’s system, interfacing with the MPU can generally be classified into the following
activities:
1. Creation of a new memory region requires loading the appropriate region descriptor into an
available register location. When a new descriptor is loaded into a RGD
n
, it would typically be
performed using four 32-bit word writes. As discussed in
Section 16.2.2.4.4, MPU Region
Summary of Contents for PXR4030
Page 1: ...PXR40 Microcontroller Reference Manual Devices Supported PXR4030 PXR4040 PXR40RM Rev 1 06 2011...
Page 30: ...PXR40 Microcontroller Reference Manual Rev 1 Freescale Semiconductor xxx...
Page 40: ...PXR40 Microcontroller Reference Manual Rev 1 xl Freescale Semiconductor...
Page 66: ...Memory Map PXR40 Microcontroller Reference Manual Rev 1 2 4 Freescale Semiconductor...
Page 120: ...Signal Descriptions 3 54 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...
Page 860: ...FlexCAN Module 24 50 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...
Page 1167: ...Decimation Filter Freescale Semiconductor 28 53 PXR40 Microcontroller Reference Manual Rev 1...
Page 1168: ...Decimation Filter 28 54 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...
