Error Correction Status Module (ECSM)
Freescale Semiconductor
17-5
PXR40 Microcontroller Reference Manual, Rev. 1
17.2.2.5
ECC Configuration Register (ECSM_ECR)
The ECC configuration register is an 8-bit control register for specifying which types of memory errors
are reported. In all systems with ECC, the occurrence of a non-correctable error causes the current access
to be terminated with an error condition. In many cases, this error termination is reported directly by the
initiating bus master. However, there are certain situations where the occurrence of this type of
non-correctable error is not reported by the master. Examples include speculative instruction fetches that
are discarded due to a change-of-flow operation and buffered operand writes. The ECC reporting logic in
the ECSM provides an optional error interrupt mechanism to signal all non-correctable memory errors. In
addition to the interrupt generation, the ECSM captures specific information (memory address, attributes
and data, bus master number, etc.) that may be useful for subsequent failure analysis.
for the ECC configuration register definition.
2
SWTR
Platform Software Watchdog Timer Reset
1 Last recorded event was a reset caused by the platform’s software watchdog timer.
3–7
Reserved
Offset: ECSM_BAS 0x0043
Access: User read/write
0
1
2
3
4
5
6
7
R
0
0
ER1BR
EF1BR
0
0
ERNCR
EFNCR
W
Reset
0
0
0
0
0
0
0
0
Figure 17-2. ECC Configuration (ECSM_ECR) Register
Table 17-4. ECSM_ECR Field Descriptions
Field
Description
0–1
Reserved
2
ER1BR
Enable RAM 1-bit reporting.
0 Reporting of single-bit RAM corrections is disabled.
1 Reporting of single-bit RAM corrections is enabled.
The occurrence of a single-bit RAM correction generates an ECSM ECC interrupt request as signalled by the
assertion of ECSM_ESR[R1BC]. The address, attributes and data are also captured in the ECSM_REAR,
ECSM_RESR, ECSM_REMR, ECSM_REAT and ECSM_REDR registers.
3
EF1BR
Enable flash 1-bit reporting.
0 Reporting of single-bit flash corrections is disabled.
1 Reporting of single-bit flash corrections is enabled.
The occurrence of a single-bit flash correction generates a MCM ECC interrupt request as signalled by the assertion
of ECSM_ESR[F1BC]. The address, attributes and data are also captured in the ECSM_FEAR, ECSM_FEMR,
ECSM_FEAT and ECSM_FEDR registers.
4–5
Reserved
Table 17-3. Miscellaneous Reset Status Register (ECSM_MRSR) Field Descriptions (continued)
Field
Description
Summary of Contents for PXR4030
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