Error Correction Status Module (ECSM)
Freescale Semiconductor
17-7
PXR40 Microcontroller Reference Manual, Rev. 1
If both a flash and RAM non-correctable error occur at the same time, the ECSM records the event with
the highest priority, RNCE, and finally FNCE. If both a 512K and 80K RAM non-correctable error occur
at the same time, the ECSM records the event with the 512K array.
17.2.2.7
ECC Error Generation Register (ECSM_EEGR)
The ECC error generation register is a 16-bit control register used to force the generation of single- and
double-bit data inversions in the memories with ECC, most notably the RAM. This capability is provided
for two purposes:
•
It provides a software-controlled mechanism for injecting errors into the memories during data
writes to verify the integrity of the ECC logic.
•
It provides a mechanism to allow testing of the software service routines associated with memory
error logging.
The intent is to generate errors during data write cycles, such that subsequent reads of the corrupted
address locations generate ECC events, either single-bit corrections or double-bit noncorrectable errors
that are terminated with an error response.
Table 17-5. ECSM_ESR Field Descriptions
Field
Description
0–1
Reserved
2
R1BC
RAM 1-bit Correction. This bit can only be set if ECSM_ECR[EPR1BR] is asserted. The occurrence of a
properly-enabled single-bit RAM correction generates an ECSM ECC interrupt request. The address, attributes
and data are also captured in the ECSM_REAR, ECSM_RESR, ECSM_REMR, ECSM_REAT and ECSM_REDR
registers. To clear this interrupt flag, write a 1 to this bit. Writing a 0 has no effect
0 No reportable single-bit RAM correction has been detected.
1 A reportable single-bit RAM correction has been detected.
3
F1BC
Flash 1-bit Correction. This bit can only be set if ECSM_ECR[EPF1BR] is asserted. The occurrence of a
properly-enabled single-bit flash correction generates an ECSM ECC interrupt request. The address, attributes
and data are also captured in the ECSM_FEAR, ECSM_FEMR, ECSM_FEAT and ECSM_FEDR registers. To
clear this interrupt flag, write a 1 to this bit. Writing a 0 has no effect.
0 No reportable single-bit flash correction has been detected.
1 A reportable single-bit flash correction has been detected.
4–5
Reserved
6
RNCE
RAM Non-Correctable Error. The occurrence of a properly-enabled non-correctable RAM error generates an
ECSM ECC interrupt request. The faulting address, attributes, and data in either the 512K or 80K array are also
captured in the ECSM_REAR, ECSM_RESR, ECSM_REMR, ECSM_REAT, and ECSM_REDR registers. To
clear this interrupt flag, write a 1 to this bit. Writing a 0 has no effect.
0 No reportable non-correctable RAM error has been detected.
1 A reportable non-correctable RAM error has been detected.
7
FNCE
Flash Non-Correctable Error. The occurrence of a properly-enabled non-correctable flash error generates an
ECSM ECC interrupt request. The faulting address, attributes and data are also captured in the ECSM_FEAR,
ECSM_FEMR, ECSM_FEAT, and ECSM_FEDR registers. To clear this interrupt flag, write a 1 to this bit. Writing
a 0 has no effect.
0 No reportable non-correctable flash error has been detected.
1 A reportable non-correctable flash error has been detected.
Summary of Contents for PXR4030
Page 1: ...PXR40 Microcontroller Reference Manual Devices Supported PXR4030 PXR4040 PXR40RM Rev 1 06 2011...
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