Error Correction Status Module (ECSM)
Freescale Semiconductor
17-9
PXR40 Microcontroller Reference Manual, Rev. 1
NOTE
If an attempt to force a non-correctable inversion by asserting
ECSM_EEGR[FRCNCI] or ECSM_EEGR[FRC1NCI], and
ECSM_EEGR[ERRBIT] equals 64, no data inversion is generated.
The only allowable values for the 4 control bit enables {FR11BI, FRC1BI,
FRCNCI, FR1NCI} are {0,0,0,0}, {1,0,0,0}, {0,1,0,0}, {0,0,1,0} and
{0,0,0,1}. All other values result in undefined behavior.
17.2.2.8
Flash ECC Address Register (ECSM_FEAR)
The ECSM_FEAR is a 32-bit register for capturing the address of the last, properly-enabled ECC event in
the flash memory. Depending on the state of the ECC configuration register, an ECC event in the flash
causes the address, attributes and data associated with the access to be loaded into the ECSM_FEAR,
ECSM_FEMR, ECSM_FEAT, and ECSM_FEDR registers and also the appropriate flag (F1BC or FNCE)
in the ECC status register to be asserted.
7
FR1NC
Force RAM One Noncorrectable Data Inversions. The assertion of this bit forces the RAM controller to create one
2-bit data inversion, as defined by the bit position specified in ERRBIT and the overall odd parity bit, on the first write
operation after this bit is set.
The normal ECC generation takes place in the RAM controller, but then the polarity of the bit position defined by
ERRBIT and the overall odd parity bit are inverted to introduce a 2-bit ECC error in the RAM.
After this bit has been enabled to generate a single 2-bit error, it must be cleared before being set again to properly
re-enable the error generation logic.
0 No RAM single 2-bit data inversions are generated.
1 One 2-bit data inversion in the RAM is generated.
8
Reserved
9–15
ERRBIT
Error Bit Position. The vector defines the bit position, which is complemented to create the data inversion on the
write operation. For the creation of 2-bit data inversions, the bit specified by this field plus the odd parity bit of the
ECC code are inverted.
The platform RAM controller follows a vector bit ordering scheme where LSB = 0. Errors in the ECC syndrome bits
can be generated by setting this field to a value greater than the RAM width. For example, consider a 64-bit RAM
implementation.
The 64-bit ECC approach requires 8 code bits for a 64-bit double word. For PRAM data width of 64 bits, the actual
SRAM 64b data + 8b for ECC = 72 bits. The following association between the ERRBIT field and the corrupted
memory bit is defined:
if ERRBIT = 0, then RAM[0] is inverted
if ERRBIT = 1, then RAM[1] is inverted
...
if ERRBIT = 63, then RAM[63] is inverted
if ERRBIT = 64,then ECC Parity[0] is inverted
if ERRBIT = 65,then ECC Parity[1] is inverted
...
if ERRBIT = 71,then ECC Parity[7] is inverted
Table 17-6. ECSM_EEGR Field Descriptions (continued)
Field
Description
Summary of Contents for PXR4030
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