Freescale Semiconductor
18-1
PXR40 Microcontroller Reference Manual, Rev. 1
Chapter 18
Software Watchdog Timer (SWT)
18.1
Introduction
18.1.1
Overview
The Software Watchdog Timer (SWT) is a peripheral module that can prevent system lockup in situations
such as software getting trapped in a loop or if a bus transaction fails to terminate. When enabled, the SWT
require periodic execution of a watchdog servicing operation. The servicing operation resets the timer to
a specified time-out period. If this servicing action does not occur before the timer expires the SWT
generates an interrupt or hardware reset. The SWT can be configured to generate a reset or interrupt on an
initial time-out; a reset is always generated on a second consecutive time-out.
The SWT interrupt is ‘ORed’ with the critical interrupt signal from the SIU and routed to the critical
interrupt inputs of the CPU; see the SIU chapter for details.
The SWT includes an interrupt status bit so the ISR software can determine if the critical interrupt request
came from the SWT or the external critical interrupt pin (WKPCFG_GPIO213).
The SWT can assert a reset when the watchdog timer expires. This reset will cause a system reset
equivalent to assertion of the RESET pin. Bit 6 of the Reset Status Register in the SIU indicates the SWT
as the source of the last reset.
18.1.2
Features
The SWT has the following features:
•
32-bit time-out register to set the time-out period
•
Programmable selection of system or oscillator clock for timer operation
•
Programmable selection of window mode or regular servicing
•
Programmable selection of reset or interrupt on an initial time-out
•
Programmable selection of fixed or keyed servicing
•
Master access protection
•
Hard and soft configuration lock bits
18.1.3
Modes of Operation
The SWT supports three device modes of operation: normal, debug and stop. When the SWT is enabled
in normal mode, its counter runs continuously. In debug mode, operation of the counter is controlled by
the FRZ bit in the SWT_MCR. If the FRZ bit is set, the counter is stopped in debug mode, otherwise it
Summary of Contents for PXR4030
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