Software Watchdog Timer (SWT)
Freescale Semiconductor
18-9
PXR40 Microcontroller Reference Manual, Rev. 1
18.4
Functional Description
The SWT is a 32-bit timer designed to enable the system to recover in situations such as software getting
trapped in a loop or if a bus transaction fails to terminate. It includes a control register (SWT_MCR), an
interrupt register (SWT_IR), a time-out register (SWT_TO), a window register (SWT_WN), a service
register (SWT_SR), a counter output register (SWT_CO) and a service key register (SWT_SK).
The SWT_MCR includes bits to enable the timer, set configuration options and lock configuration of the
module. The watchdog is enabled by setting the SWT_MCR[WEN] bit. The watchdog starts operation
automatically after reset is released (WEN=1).
The SWT_TO register holds the watchdog time-out period in clock cycles unless the value is less than
0x100 in which case the time-out period is set to 0x100. This time-out period is loaded into an internal
32-bit down counter when the SWT is enabled and each time a valid service operation is performed. The
SWT_MCR[CSL] bit selects which clock (system or oscillator) is used to drive the down counter.
The configuration of the SWT can be locked through use of either a soft lock or a hard lock. In either case,
when locked the SWT_MCR, SWT_TO, SWT_WN and SWT_SK registers are read only. The hard lock
is enabled by setting the SWT_MCR[HLK] bit which can only be cleared by a reset. The soft lock is
enabled by setting the SWT_MCR[SLK] bit and is cleared by writing the unlock sequence to the service
register. The unlock sequence is a write of 0xC520 followed by a write of 0xD928 to the SWT_SR[WSC]
field. There is no timing requirement between the two writes. The unlock sequence logic ignores service
sequence writes and recognizes the 0xC520, 0xD928 sequence regardless of previous writes. The unlock
sequence can be written at any time and does not require the SWT_MCR[WEN] bit to be set.
When enabled, the SWT requires periodic execution of a servicing operation which consists of writing two
values to the SWT_SR. Writing the proper sequence of values loads the internal down counter with the
time-out period. There is no timing requirement between the two writes and the service sequence logic
ignores unlock sequence writes. If the SWT_MCR[KEY] bit is zero, the fixed sequence 0xA602, 0xB480
is written to the SWT_SR[WSC] field to service the watchdog. If the SWT_MCR[KEY] bit is set, then
two pseudorandom keys are written to the SWT_SR[WSC] field to service the watchdog. The key values
are determined by the pseudorandom key generator defined in
. This algorithm will generate a
sequence of 2
16
different key values before repeating. The state of the key generator is held in the
SWT_SK register. For example, if SWT_SK[SK] is 0x0100 then the service sequence keys are 0x1103,
0x2136. In this mode, each time a valid key is written to the SWT_SR register, the SWT_SK register is
updated. So, after servicing the watchdog by writing 0x1103 and then 0x2136 to the SWT_SR[WSC] field,
SWT_SK[SK] is 0x2136 and the next key sequence is 0x3499, 0x7E2C.
Figure 18-8. Pseudorandom Key Generator
Accesses to SWT registers occur with no peripheral bus wait states. (The peripheral bus bridge may add
one or more system wait states.) However, due to synchronization logic in the SWT design, recognition of
the service sequence or configuration changes may require up to three system plus seven counter clock
cycles.
SK
n+1
= (17*SK
n
+3) mod 2
16
Summary of Contents for PXR4030
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