Periodic Interrupt Timer (PIT_RTI)
Freescale Semiconductor
20-9
PXR40 Microcontroller Reference Manual, Rev. 1
20.4.2
Interrupts
All of the timers support interrupt generation. Refer to
Section 10.4.1, Interrupt Request Sources
, for
related vector addresses and priorities.
Timer interrupts can be disabled by setting the timer PIT_CH
n
_TCTRL[TIE] bit to zero. The
PIT_CH
n
_TFLG[TIF] bit is set to 1 when a timeout occurs on the associated timer, and is cleared by
writing a 1 to that bit.
20.5
Initialization and Application Information
20.5.1
Example Configuration
In the example configuration:
•
the PIT clock has a frequency of 50 MHz
•
timer 1 shall create an interrupt every 5.12 ms
First the PIT module is activated by writing a 0 to the MDIS bit in the PITCTRL register.
The 50 MHz clock frequency equates to a clock period of 20 ns. Timer 1 needs to trigger every 5.12 ms/20
ns = 256000 cycles. The value for the LDVAL register trigger would be calculated as (period / clock
period) -1.
This means that PIT_PIT_CH1_LDVAL with 0003E7FF hex.
The interrupt for Timer 1 is enabled by setting PIT_CH1_TCTRL[TIE] bit. The timer is started by writing
a 1 to the PIT_CH1_TCTRL[TEN] bit.
The following example pseudo-code matches the described setup:
// turn on PIT
PIT_MCR = 0x00;
// RTI
PIT_RTI_LDVAL = 0x004C4B3F; // setup RTI for 5000000 cycles
PIT_RTI_TCTRL[TIE] = 1; // let RTI generate interrupts
PIT_RTI_TCTRL[TEN] = 1; // start RTI
// Timer 1
PIT_CH1_LDVAL = 0x0003E7FF; // setup timer 1 for 256000 cycles
PIT_CH1_TCTRL[TIE] = 1; // enable Timer 1 interrupts
PIT_CH1_TCTRL[TEN] = 1; // start timer 1
20.5.2
Low Power Mode – Using the RTI for System Wakeup
This section describes the use of the low power mode, both with and without use of the RTI timer for
wakeup.
Summary of Contents for PXR4030
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