Enhanced Direct Memory Access Controller (eDMA)
Freescale Semiconductor
21-13
PXR40 Microcontroller Reference Manual, Rev. 1
21.3.2
Register Descriptions
NOTE
Any reference to EDMA_A_[register_name] should be ignored when using
eDMA_B. That register does not exist in eDMA_B. Registers that exist in
both eDMA_A and eDMA_B are indicated with a register name of format
EDMA_
x
_[register_name].
This section lists the eDMA registers in address order and describes the registers and their bit fields.
Reading reserved bits in a register returns the value of zero. Writes to reserved bits in a register are ignored.
Reading or writing to a reserved memory location generates a bus error.
Many of the control registers have a bit width that matches the number of channels implemented in the
module:
•
64 bits for eDMA_A (made up of two 32-bit registers: high and low—for example
EDMA_A_ERQRH has upper 32 channels of eDMA_A)
•
32 bits for eDMA_B
21.3.2.1
eDMA Control Register (EDMA_x_MCR)
The 32-bit EDMA_
x
_MCR defines the basic operating configuration of the eDMA.
The eDMA arbitrates channel service requests in two (eDMA_B) or four (eDMA_A) groups (0, 1, 2, 3) of
16 channels each:
•
Group 0 contains channels 0–15
•
Group 1 contains channels 16–31
•
Group 2 contains channels 32-47 (eDMA_A only)
•
Group 3 contains channels 48-63 (eDMA_A only)
Arbitration within a group can be configured to use a fixed priority or a round robin. In fixed-priority
arbitration, the highest priority channel requesting service is selected to execute. The priorities are
0xFFF5_411C
eDMA Channel 28
Priority
(EDMA_B_CPR28)
eDMA Channel 29
Priority
(EDMA_B_CPR29)
eDMA Channel 30
Priority
(EDMA_B_CPR30)
eDMA Channel 31
Priority
(EDMA_B_CPR31)
0xFFF5_4120 –
0xFFF5_4FFF
Reserved
0xFFF5_5000 –
0xFFF5_51FC
EDMA_B_TCD00–EDMA_B_TCD15
0xFFF5_5200 –
0xFFF5_53FC
EDMA_B_TCD16–EDMA_B_TCD31
0xFFF5_5300
Reserved
Table 21-3. eDMA_B 32-bit Memory Map—Graphical View (continued)
Address
Register
Summary of Contents for PXR4030
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