FlexRay Communication Controller (FLEXRAY)
22-12
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
reset conditions are mentioned in the detailed description of the register. The additional reset conditions
are explained in
22.5.2.2
Register Write Access
This section describes the write access restriction terms that apply to all registers.
22.5.2.2.1
Register Write Access Restriction
For each register bit and register field, the write access conditions are specified in the detailed register
description. A description of the write access conditions is given in
bit or field, none of the given write access conditions is fulfilled, any write attempt to this register bit or
field is ignored without any notification. The values of the bits or fields are not changed. The condition
term [A or B] indicates that the register or field can be written to if at least one of the conditions is fulfilled.
22.5.2.2.2
Register Write Access Requirements
All registers can be accessed with 8-bit, 16-bit and 32-bit wide operations. For some of the registers, at
least a 16-bit wide write access is required to ensure correct operation. This write access requirement is
stated in the detailed register description for each register affected
22.5.2.2.3
Internal Register Access
The following memory mapped registers are used to access multiple internal registers.
•
Strobe Signal Control Register (STBSCR)
•
Slot Status Selection Register (SSSR)
•
Slot Status Counter Condition Register (SSCCR)
•
Receive Shadow Buffer Index Register (RSBIR)
Table 22-5. Additional Register Reset Conditions
Condition
Description
Protocol RUN Command
The register field is reset when the application writes to RUN command “0101” to the
POCCMD field in the
Protocol Operation Control Register (POCR)
.
Message Buffer Disable
The register field is reset when the application has disabled the message buffer.
This happens when the application writes 1 to the message buffer disable trigger bit
MBCCSRn[EDT] while the message buffer is enabled (MBCCSn[EDS] = 1) and the
controller grants the disable to the application by clearing the MBCCSRn[EDS] bit.
Table 22-6. Register Write Access Restrictions
Condition
Indication
Description
Any Time
—
No write access restriction.
Disabled Mode
MCR[MEN] = 0
Write access only when the controller is in Disabled Mode.
Normal Mode
MCR[MEN] = 1
Write access only when the controller is in Normal Mode.
POC:config
PSR0[PROTSTATE] =
POC:config
Write access only when the Protocol is in the
POC:config
state.
MB_DIS
MBCCSR[EDS] = 0
Write access only when the related Message Buffer is disabled.
MB_LCK
MBCCSRn[LCKS] = 1
Write access only when the related Message Buffer is locked.
Summary of Contents for PXR4030
Page 1: ...PXR40 Microcontroller Reference Manual Devices Supported PXR4030 PXR4040 PXR40RM Rev 1 06 2011...
Page 30: ...PXR40 Microcontroller Reference Manual Rev 1 Freescale Semiconductor xxx...
Page 40: ...PXR40 Microcontroller Reference Manual Rev 1 xl Freescale Semiconductor...
Page 66: ...Memory Map PXR40 Microcontroller Reference Manual Rev 1 2 4 Freescale Semiconductor...
Page 120: ...Signal Descriptions 3 54 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...
Page 860: ...FlexCAN Module 24 50 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...
Page 1167: ...Decimation Filter Freescale Semiconductor 28 53 PXR40 Microcontroller Reference Manual Rev 1...
Page 1168: ...Decimation Filter 28 54 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...
