Enhanced Modular Input/Output Subsystem (eMIOS200)
23-36
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
Figure 23-30. QDEC Example with Phase_A & Phase_B Encoder
23.4.1.1.10
Windowed Programmable Time Accumulation (WPTA) Mode
The WPTA mode (MODE = 000_1110) accumulates the sum of the total high time or low time of an input
signal over a programmable interval (time window).
The UCPRE[1:0] prescaler bits in the EMIOS_CCR[
n
] register define the increment rate of the internal
counter.
Register A1 holds the start time and register B1 holds the stop time of the programmable time interval.
When a match occurs between register A (EMIOS_CADR) and the selected timebase, the internal counter
is cleared and it is ready to start counting. The internal counter is used as a time accumulator, i.e., it counts
up when the input signal has the same polarity of the EDPOL bit in the EMIOS_CCR[
n
] register and does
not count otherwise. When a match occurs in comparator B, the internal counter is disabled regardless of
the input signal polarity and the FLAG bit is set. At the same time, the contents of the EMIOS_CCNTR[
n
]
register is transferred to register A2. Reading registers EMIOS_CCNTR[
n
] or A2 returns the high or low
time of the input signal.
Note that EMIOS_CCNTR[
n
] is stable only outside the time window defined from A1 to B1 matches.
Otherwise, its contents reflect a count in progress and not the final value. Alternatively to
EMIOS_CCNTR[
n
], register A2 returns the latest available measurement. Since this register is updated
only at comparator B matches, it always contains stable and up-to-date data. In this mode, this register is
accessible through the alternate register address EMIOS_ALTA[
n
].
shows how the unified channel can be used to accumulate high time.
Note: EMIOS_CADR[n] = A1
+1 +1 +1 +1 +1 +1 +1 +1
–1 –1 –1 –1 –1
+1 +1 +1 +1 +1 +1
–1
EMIOS_CCNTR[n]
Phase A (from UC[n])
Phase B (from UC[n – 1])
0x000000
EMIOS_CCNTR[n]
Time
FLAG Pin/Register
Value 2
Value 1
–1
+1
+1
–1 –1 –1 –1 –1
+1 +1 +1 +1 +1 +1
–1
–1
+1
MODE[6] = 1
A1 Write
(Value 1)
A1 Match
A1 Match
A1 Match
A1 Match
A1 Match
A1 Write
(Value 2)
inc/dec
Summary of Contents for PXR4030
Page 1: ...PXR40 Microcontroller Reference Manual Devices Supported PXR4030 PXR4040 PXR40RM Rev 1 06 2011...
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Page 120: ...Signal Descriptions 3 54 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...
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Page 1167: ...Decimation Filter Freescale Semiconductor 28 53 PXR40 Microcontroller Reference Manual Rev 1...
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