FlexCAN Module
Freescale Semiconductor
24-45
PXR40 Microcontroller Reference Manual, Rev. 1
A direct consequence of the first requirement is that the minimum number of time quanta per CAN bit must
be 8, so the oscillator clock frequency should be at least 8 times the CAN bit rate. The minimum frequency
ratio specified in
can be achieved by choosing a high enough peripheral clock frequency when
compared to the oscillator clock frequency, or by adjusting one or more of the bit timing parameters
(PRESDIV, PROPSEG, PSEG1, PSEG2). As an example, taking the case of 64 MBs, if the oscillator and
peripheral clock frequencies are equal and the CAN bit timing is programmed to have 8 time quanta per
bit, then the prescaler factor (P 1) should be at least 2. For prescaler factor equal to one and
CAN bit timing with 8 time quanta per bit, the ratio between peripheral and oscillator clock frequencies
should be at least 2.
24.4.9
Modes of Operation Details
24.4.9.1
Freeze Mode
This mode is entered by asserting the HALT bit in the FLEXCAN_x_MCR Register or when the MCU is
put into Debug Mode. In both cases it is also necessary that the FRZ bit is asserted in the
FLEXCAN_x_MCR Register and the module is not in any of the low power modes (Disable, Stop). When
Freeze Mode is requested during transmission or reception, FlexCAN does the following:
•
Waits to be in either Intermission, Passive Error, Bus Off or Idle state
•
Waits for all internal activities like arbitration, matching, move-in and move-out to finish
•
Ignores the Rx input pin and drives the Tx pin as recessive
•
Stops the prescaler, thus halting all CAN protocol activities
•
Grants write access to the Error Counters Register, which is read-only in other modes
•
Sets the NOT_RDY and FRZ_ACK bits in FLEXCAN_x_MCR
After requesting Freeze Mode, the user must wait for the FRZ_ACK bit to be asserted in
FLEXCAN_x_MCR before executing any other action, otherwise FlexCAN may operate in an
unpredictable way. In Freeze mode, all memory mapped registers are accessible.
Exiting Freeze Mode is done in one of the following ways:
•
CPU negates the FRZ bit in the FLEXCAN_x_MCR Register
•
The MCU is removed from Debug Mode and/or the HALT bit is negated
Once out of Freeze Mode, FlexCAN tries to re-synchronize to the CAN bus by waiting for 11 consecutive
recessive bits.
Table 24-21. Minimum Ratio Between Peripheral Clock Frequency and CAN Bit Rate
Number of Message
Buffers
Minimum Ratio
16
8
32
8
64
16
Summary of Contents for PXR4030
Page 1: ...PXR40 Microcontroller Reference Manual Devices Supported PXR4030 PXR4040 PXR40RM Rev 1 06 2011...
Page 30: ...PXR40 Microcontroller Reference Manual Rev 1 Freescale Semiconductor xxx...
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Page 120: ...Signal Descriptions 3 54 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...
Page 860: ...FlexCAN Module 24 50 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...
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