Deserial Serial Peripheral Interface (DSPI)
Freescale Semiconductor
25-7
PXR40 Microcontroller Reference Manual, Rev. 1
25.2.2.3
PCS[4]/MTRIG — Peripheral Chip Select 4/Master Trigger
NOTE
MTRIG is an internal connection and not available on a pin.
In Master Mode, PCS[4] is a Peripheral Chip Select output signal.
In Slave Mode, MTRIG is an output trigger signal that indicates that a change in data to be serialized has
occurred. The MTRIG provides a pulse in DSI Configuration when a change in data to be serialized occurs.
The MTRIG pulse is four system clock cycles in duration. If the DSPI is in Slave Mode and the MTO is
disabled, the PCS[4]/MTRIG signal is unused.
25.2.2.4
PCS[5]/PCSS — Peripheral Chip Select 5/Peripheral Chip Select Strobe
PCS[5] is a Peripheral Chip Select output signal. When the DSPI is in Master Mode and PCSSE bit in the
DSPI_MCR is negated, this signal is used to select which slave device the current transfer is intended for.
PCSS provides a strobe signal that can be used with an external demultiplexer for deglitching of the PCS
signals. When the DSPI is in Master Mode and the PCSSE bit in the DSPI_MCR is set, the PCSS provides
the appropriate timing for the decoding of the PCS[0] - PCS[4] and PCS[6] - PCS[7] signals which
prevents glitches from occurring.
This signal is not used in Slave Mode.
25.2.2.5
SIN — Serial Input
SIN is a serial data input signal.
25.2.2.6
SOUT — Serial Output
SOUT is a serial data output signal.
25.2.2.7
SCK — Serial Clock
SCK is a serial communication clock signal. In Master Mode, the DSPI generates the SCK. In Slave Mode,
SCK is an input from an external bus master.
25.2.2.8
HT — Hardware Trigger
HT is an internal connection and not available on a pin.
HT is a trigger input signal to the DSPI module that is used with Multiple Transfer Operations in DSI
Configuration.
In Master Mode while in DSI or CSI Configurations, the HT signal initiates a data transfer when the TRRE
bit in the DSPI_DSICR is set and a rising or falling edge is detected on HT. Which edge to trigger on is
determined by the TPOL bit in the DSPI_DSICR.
Summary of Contents for PXR4030
Page 1: ...PXR40 Microcontroller Reference Manual Devices Supported PXR4030 PXR4040 PXR40RM Rev 1 06 2011...
Page 30: ...PXR40 Microcontroller Reference Manual Rev 1 Freescale Semiconductor xxx...
Page 40: ...PXR40 Microcontroller Reference Manual Rev 1 xl Freescale Semiconductor...
Page 66: ...Memory Map PXR40 Microcontroller Reference Manual Rev 1 2 4 Freescale Semiconductor...
Page 120: ...Signal Descriptions 3 54 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...
Page 860: ...FlexCAN Module 24 50 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...
Page 1167: ...Decimation Filter Freescale Semiconductor 28 53 PXR40 Microcontroller Reference Manual Rev 1...
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