Deserial Serial Peripheral Interface (DSPI)
Freescale Semiconductor
25-47
PXR40 Microcontroller Reference Manual, Rev. 1
25.4.6.4
Delay after Transfer (t
DT
)
The Delay after Transfer is the length of time between negation of the PCS signal for a frame and the
assertion of the PCS signal for the next frame. See
for an illustration of the Delay after
Transfer. The PDT and DT fields in the DSPI_CTAR
x
registers select the Delay after Transfer by the
formula in the DT[0:3] field description.
shows an example of how to compute the Delay after
Transfer.
When in non-continuous clock mode the t
DT
delay is configurable as outlined in the DSPI_CTARx
registers. When in continuous clock mode and TSB is not enabled the delay is fixed at 1 SCK period. When
in TSB and continuous mode the delay is programmed as outlined in the DSPI_CTARx registers but in the
event that the delay does not coincide with an SCK period in duration the delay is extended to the next
SCK active edge.
shows an example of how to compute the Delay after Transfer with the clock
period of SCK defined as T
SCK
. The values calculated assume 1 TSCK period = 4 ipg_clk.
Table 25-31. Delay after Transfer Computation Example
PDT
Prescaler
DT
Scaler
f
periph
Delay after Transfer
0b01
3
0b1110
32768
100 MHz
0.98 ms
Table 25-32. Delay after Transfer Computation Example in TSB Configuration
PDT field
t
DT
1
(Tsck)
0
1
2
3
DT field
0
2
1
2
3
4
1
1
3
5
7
2
2
6
10
14
3
4
12
20
28
4
8
24
40
56
5
16
48
80
112
6
32
96
160
224
7
64
192
320
448
8
128
384
640
896
9
256
768
1280
1792
10
512
1536
2560
3584
11
1024
3072
5120
7168
12
2048
6144
10240
14336
13
4096
12288
20480
28672
14
8192
24576
40960
57344
15
16384
49152
81920
114688
Summary of Contents for PXR4030
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