Enhanced Queued Analog-to-Digital Converter (EQADC)
27-4
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
shows the primary components inside the EQADC.
also depicts data flow through the EQADC. Commands are contained in system memory in a
user defined data structure. The most likely data structure to be used is a queue (as shown in
).
Command data is moved from the command queue (CQueue) to the CFIFOs by either the host CPU or by
the system DMA controller. Once a CFIFO is triggered and becomes the highest priority CFIFO using a
certain CBuffer, command data is transferred from the CFIFO to the on-chip ADCs. The ADC executes
the command, and the result is moved through the
Result Format and Calibration Sub-Block
to either the
side interface or to the RFIFO. Data from the on-chip companion module (decimation filter) bypasses the
Result Format and Calibration Sub-Block
and is moved directly to its specified RFIFO. When data is
stored in an RFIFO, data is moved from the RFIFO by the host CPU or by the system DMA controller to
a data structure in system memory as a result queue (RQueue).
If you are familiar with the QADC, the EQADC system upgrades the functionality provided by that block.
Refer to
Section 27.8.7, EQADC Versus QADC
, for a comparison between the EQADC and QADC.
27.2.1
Features
Each EQADC block includes these distinctive features (except where noted):
Table 27-1. EQADC Primary Component Descriptions
Component
Function
FIFO Control Unit
Controls the CFIFOs and the RFIFOs:
• Prioritizes the CFIFOs to determine which CFIFOs will have their
commands transferred.
• Supports software and hardware triggers to start command transfers from a
particular CFIFO.
• Decodes command data from the CFIFOs and, accordingly, sends these
commands to one of the two on-chip ADCs.
• Decodes result data from on-chip ADCs and transfers data to the
appropriate RFIFO or to the parallel side interface.
ADC Control Logic
Manages the execution of commands bound for on-chip ADCs:
• interfaces with the CFIFOs via two 2-entry command buffers (CBuffers) with
abort control and with the RFIFOs via the Result Format and Calibration
Sub-Block.
• Buffers command data for execution.
• Decodes command data and, accordingly, generates control signals for the
two on-chip ADCs.
• Detects abort requests, stores aborted commands and buffers immediate
conversion commands.
• Formats and calibrates conversion result data coming from the on-chip
ADCs.
• Generates the internal multiplexer control signals and the select signals
used by the external multiplexers.
EQADC Parallel Side Interface (EQADC PSI)
Allows for a full duplex, synchronous, parallel communication between the
EQADC and decimation filters.
1.
Command and result data can be stored in system memory in any user defined data structure. However, in this document
it will be assumed that the data structure of choice is a queue, since it is the most likely data structure to be used and
because queues are the only type of data structure supported by the DMAC.
Summary of Contents for PXR4030
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