3.2 Operating Mode (SW2)
SW2
DIP switch
setting
Logical value
Description
Boot signal (SW2/1)
ON
0 (low)
Boot signal
MD2 (SW2/2)
ON
0 (low)
MD1 (SW2/3)
ON
0 (low)
MD0 (SW2/4)
ON
0 (low)
Internal ROM mode
3.3 UART (JP21, JP22)
Jumper setting
Description
ON (closed)
UART0 Output enable
SOT_0
(JP21)
OFF (open)
UART0 Output disable
Jumper setting
Description
ON (closed)
UART0 Input enable
SIN_0
(JP22)
OFF (open)
UART0 Input disable
Reserved future extension:
Description
SIN_2
(JP7)
UART2 Input enable
Description
SOT_2
(JP8)
UART2 Output enable
Description
UART2 clock
(JP9)
UART2 clock enable
3.4 Chip select enable for FLASH (JP10)
CS Jumper
setting
Description
CS2
ON (closed 1-2)
Ext. Flash – Chip-Select2
CS3
ON (closed 2-3)
Ext. Flash – Chip-Select 3
7
Summary of Contents for CPU369-Module
Page 12: ...5 Schematics and Drawings 12 ...
