71
71
71
71
L E D D I S P L A Y
Base Address: E8
H
(1) LED display data registers
The double 7-segment LED display is controlled by two 8-bits wide, write-only
registers LEDDR0 and LEDDR1.
LEDDR0
[7:0]
7
6
5
4
3
2
1
0
Address: E8
H
1H
1G
1F
1E
1D
1C
1B
1A
Read/Write
W
W
W
W
W
W
W
W
Initial Value
(X)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
LEDDR1
[7:0]
7
6
5
4
3
2
1
0
Address: E9
H
2H
2G
2F
2E
2D
2C
2B
2A
Read/Write
W
W
W
W
W
W
W
W
Initial Value
(X)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
I
f a bit in this register is ‘0’, the corresponding LED display segment is ON. E.g.,
clearing bit 2 of the LEDDR1 register will switch the segment 2C on.
The segment annotation is standard:
F P G A E E P R O M
The FPGA is configured from the AT17C256 serial configuration EEPROM
memory everytime the power is applied to the board or the board is restarted by
the Mainboard reset button. To modify the content of the FPGA EEPROM, the
following steps must be done:
1.
On the mainboard, place a jumper to the J4 position. This will set the
FPGA EEPROM to the special programming mode. While in this mode,
the EEPROM can't be used as a FPGA configuration memory - it
behaves as a standard, 256kbit I2C EEPROM memory. Therefore, if the
2A
2B
2C
2D
2E
2F
2H
1B
1C
1D
1E
1F
1H
1A
2G
1G
