![background image](http://html.mh-extra.com/html/fujitsu/fr60lite/fr60lite_hardware-manual_119677102.webp)
87
CHAPTER 3 CPU AND CONTROL UNITS
(
φ
represents the internal base clock period.)
•
These bits are initialized to "0000
B
" at a reset (INIT).
•
A read and a write are possible.
[bit11 to bit8] P3, P2, P1, P0 (clkP divide select 3 to 0)
These bits are used to set the peripheral clock (CLKP) frequency divide ratio.
The clock frequency divide ratio set by these bits applies to the clock signal (CLKP) for peripheral circuits
and peripheral buses.
The combination of values written to these bits selects the divide ratio (clock frequency) for the peripheral
circuit/peripheral bus clock signal relative to the base clock signal, from among the 16 types listed below.
Do not set the bits to a divide ratio which results in a frequency higher than the maximum operating
frequency.
(
φ
represents the system base clock period.)
•
These bits are initialized to "0011
B
" at a reset (INIT).
•
A read and a write are possible.
B3
B2
B1
B0
Clock divide ratio
Clock frequency: Oscillation frequency
of 4 MHz and main PLL multiplier of 8×
0
0
0
0
φ
32 MHz (Initial value)
0
0
0
1
φ
× 2 (Divide by 2)
16 MHz
0
0
1
0
φ
× 3 (Divide by 3)
10.7 MHz
0
0
1
1
φ
× 4 (Divide by 4)
8 MHz
0
1
0
0
φ
× 5 (Divide by 5)
6.4 MHz
0
1
0
1
φ
× 6 (Divide by 6)
5.33 MHz
0
1
1
0
φ
× 7 (Divide by 7)
4.57 MHz
0
1
1
1
φ
× 8 (Divide by 8)
4 MHz
...
...
...
...
...
...
1
1
1
1
φ
× 16 (Divide by 16)
2 MHz
P3
P2
P1
P0
Clock divide ratio
Clock frequency: Oscillation frequency of
4 MHz and main PLL multiplier of 8×
0
0
0
0
φ
32 MHz
0
0
0
1
φ
× 2 (Divide by 2)
16 MHz
0
0
1
0
φ
× 3 (Divide by 3)
10.7 MHz
0
0
1
1
φ
× 4 (Divide by 4)
8 MHz (Initial value)
0
1
0
0
φ
× 5 (Divide by 5)
6.4 MHz
0
1
0
1
φ
× 6 (Divide by 6)
5.33 MHz
0
1
1
0
φ
× 7 (Divide by 7)
4.57 MHz
0
1
1
1
φ
× 8 (Divide by 8)
4 MHz
...
...
...
...
...
...
1
1
1
1
φ
× 16 (Divide by 16)
2 MHz
Summary of Contents for FR60Lite
Page 3: ......
Page 5: ......
Page 115: ...100 CHAPTER 3 CPU AND CONTROL UNITS ...
Page 127: ...112 CHAPTER 4 I O PORTS ...
Page 143: ...128 CHAPTER 5 INTERRUPT CONTROLLER ...
Page 155: ...140 CHAPTER 6 EXTERNAL INTERRUPT AND NMI CONTROLLER ...
Page 197: ...182 CHAPTER 9 PPG Programmable Pulse Generator ...
Page 337: ...322 CHAPTER 13 UART ...
Page 417: ...402 CHAPTER 16 DMAC DMA Controller ...
Page 445: ...430 CHAPTER 17 FLASH MEMORY ...
Page 451: ...436 CHAPTER 18 SERIAL PROGRAMMING CONNECTION ...
Page 493: ...478 APPENDIX F Precautions on Handling ...
Page 494: ...479 INDEX INDEX The index follows on the next page This is listed in alphabetic order ...
Page 507: ...492 INDEX ...
Page 509: ......