117
CHAPTER 5 INTERRUPT CONTROLLER
■
Block Diagram
Figure 5.1-2 Block Diagram
HLDREQ
cancel
request
R-bus
6
5
WAKEUP ('1'
w
hen LEVEL is not 111111
B
)
UNMI
Priority evaluation
LVL4 to LVL0
MHALTI
VCT5 to VCT0
NMI
servicing
Level/
vector
generation
RI00
•
•
•
RI47
Vector
evaluation
Level evaluation
ICR00
•
•
•
ICR47
NMI
(DLYIRQ)
Summary of Contents for FR60Lite
Page 3: ......
Page 5: ......
Page 115: ...100 CHAPTER 3 CPU AND CONTROL UNITS ...
Page 127: ...112 CHAPTER 4 I O PORTS ...
Page 143: ...128 CHAPTER 5 INTERRUPT CONTROLLER ...
Page 155: ...140 CHAPTER 6 EXTERNAL INTERRUPT AND NMI CONTROLLER ...
Page 197: ...182 CHAPTER 9 PPG Programmable Pulse Generator ...
Page 337: ...322 CHAPTER 13 UART ...
Page 417: ...402 CHAPTER 16 DMAC DMA Controller ...
Page 445: ...430 CHAPTER 17 FLASH MEMORY ...
Page 451: ...436 CHAPTER 18 SERIAL PROGRAMMING CONNECTION ...
Page 493: ...478 APPENDIX F Precautions on Handling ...
Page 494: ...479 INDEX INDEX The index follows on the next page This is listed in alphabetic order ...
Page 507: ...492 INDEX ...
Page 509: ......