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CHAPTER 6 EXTERNAL INTERRUPT AND NMI CONTROLLER
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External Interrupt Request Level
1. If the request level is an edge request, a pulse width of at least three machine cycles (peripheral clock
machine cycles) is required to detect an edge.
2. If the request input level is a level setting, a request input is entered from outside and is then cancelled,
the request to the interrupt controller remains active because a source holding circuit exists internally.
The external interrupt source register must be cleared to cancel a request to the interrupt controller.
Figure 6.3-2 Clearing the External Interrupt Source Register when a Level is Set
Figure 6.3-3 Interrupt Source and Interrupt Request to Interrupt Controller when Interrupts are Enabled
Interrupt Input
Level
detection
External interrupt source register
(Source holding circuit)
Enable gate
Interrupt controller
Holds a source unless it is cleared
Interrupt input
"H" level
Interrupt request
to interrupt controller
Becomes inactive when the external interrupt source register is cleared
Summary of Contents for FR60Lite
Page 3: ......
Page 5: ......
Page 115: ...100 CHAPTER 3 CPU AND CONTROL UNITS ...
Page 127: ...112 CHAPTER 4 I O PORTS ...
Page 143: ...128 CHAPTER 5 INTERRUPT CONTROLLER ...
Page 155: ...140 CHAPTER 6 EXTERNAL INTERRUPT AND NMI CONTROLLER ...
Page 197: ...182 CHAPTER 9 PPG Programmable Pulse Generator ...
Page 337: ...322 CHAPTER 13 UART ...
Page 417: ...402 CHAPTER 16 DMAC DMA Controller ...
Page 445: ...430 CHAPTER 17 FLASH MEMORY ...
Page 451: ...436 CHAPTER 18 SERIAL PROGRAMMING CONNECTION ...
Page 493: ...478 APPENDIX F Precautions on Handling ...
Page 494: ...479 INDEX INDEX The index follows on the next page This is listed in alphabetic order ...
Page 507: ...492 INDEX ...
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