153
CHAPTER 8 16-BIT RELOAD TIMER
8.2
16-bit Reload Timer Block Diagram
A block diagram of the reload timer is shown below.
■
Reload Timer Block Diagram
Figure 8.2-1 Block Diagram for Reload Timer
R-b
us
16-bit reload register
(TMRLR0 to TMRLR2)
16-bit do
w
n counter
(TMR0 to TMR2) UF
Count
enable
Reload
Clock selector
CSL2
CSL1
CSL0
Prescaler
IN CTL
EXCK
OUT
CTL
CSL2
CSL1
CSL0
External
trigger
selection
TO1E ,
TO2E
PFR7 bit
External timer output
TOT1(P70)
TOT2(P71)
UF
CNTE
TRG
RELD
OUTL
INTE
IRQ
External trigger input
TIN0(P51)
TIN1(P52)
TIN2(P53)
Prescaler
clear
Summary of Contents for FR60Lite
Page 3: ......
Page 5: ......
Page 115: ...100 CHAPTER 3 CPU AND CONTROL UNITS ...
Page 127: ...112 CHAPTER 4 I O PORTS ...
Page 143: ...128 CHAPTER 5 INTERRUPT CONTROLLER ...
Page 155: ...140 CHAPTER 6 EXTERNAL INTERRUPT AND NMI CONTROLLER ...
Page 197: ...182 CHAPTER 9 PPG Programmable Pulse Generator ...
Page 337: ...322 CHAPTER 13 UART ...
Page 417: ...402 CHAPTER 16 DMAC DMA Controller ...
Page 445: ...430 CHAPTER 17 FLASH MEMORY ...
Page 451: ...436 CHAPTER 18 SERIAL PROGRAMMING CONNECTION ...
Page 493: ...478 APPENDIX F Precautions on Handling ...
Page 494: ...479 INDEX INDEX The index follows on the next page This is listed in alphabetic order ...
Page 507: ...492 INDEX ...
Page 509: ......