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263
CHAPTER 11 MULTIFUNCTIONAL TIMER
Figure 11.6-5 Operation in Up/Down Count Mode when Compare Clear Buffer Is Enabled
(TCCSL Register’s BFE: Bit7 = 1)
Re
s
et
Comp
a
re cle
a
r
bu
ffer regi
s
ter
BFFF
H
Comp
a
re cle
a
r
regi
s
ter
Timer
7FFF
H
FFFF
H
BFFF
H
3
FFF
H
0000
H
Co
u
nt v
a
l
u
e
S
t
a
rt timer oper
a
tion
Zero detection
Comp
a
re cle
a
r m
a
tch
7FFF
H
FFFF
H
BFFF
H
7FFF
H
FFFF
H
Summary of Contents for FR60Lite
Page 3: ......
Page 5: ......
Page 115: ...100 CHAPTER 3 CPU AND CONTROL UNITS ...
Page 127: ...112 CHAPTER 4 I O PORTS ...
Page 143: ...128 CHAPTER 5 INTERRUPT CONTROLLER ...
Page 155: ...140 CHAPTER 6 EXTERNAL INTERRUPT AND NMI CONTROLLER ...
Page 197: ...182 CHAPTER 9 PPG Programmable Pulse Generator ...
Page 337: ...322 CHAPTER 13 UART ...
Page 417: ...402 CHAPTER 16 DMAC DMA Controller ...
Page 445: ...430 CHAPTER 17 FLASH MEMORY ...
Page 451: ...436 CHAPTER 18 SERIAL PROGRAMMING CONNECTION ...
Page 493: ...478 APPENDIX F Precautions on Handling ...
Page 494: ...479 INDEX INDEX The index follows on the next page This is listed in alphabetic order ...
Page 507: ...492 INDEX ...
Page 509: ......