![background image](http://html.mh-extra.com/html/fujitsu/fr60lite/fr60lite_hardware-manual_119677295.webp)
280
CHAPTER 11 MULTIFUNCTIONAL TIMER
*1: It is necessary to activate PPG 0 beforehand.
*2: In order to generate a non-overlapping signal, first select 2-channel mode (compare control register
higher-order (OCSH1, OCSH3, and OCSH5) CMOD: bit12 = 1) for RT1, RT3, and RT5.
*3: The GATE signal is generated from the RTx whose GTENx bit is set to "1".
*4: The GATE signal is generated while the timer activated by the RTx whose GTENx bit is set to "1" is
operating. If more than one GATEx bit is set to "1", the GATE signal is the OR of the signals for each
of the operating timers.
Note:
RTO0 and RTO1 are controlled by the 16-bit dead timer control register's higher order (DTCR0)
TMD2 to TMD0: bit10 to bit8; RTO2 and RTO3 are controlled by lower-order register's (DTCR1)
TMD5 to TMD3: bit2 to bit0; and RTO4 and RTO5 are controlled by the higher-order register's
(DTCR2) TMD8 to TMD6: bit10 to bit8.
Summary of Contents for FR60Lite
Page 3: ......
Page 5: ......
Page 115: ...100 CHAPTER 3 CPU AND CONTROL UNITS ...
Page 127: ...112 CHAPTER 4 I O PORTS ...
Page 143: ...128 CHAPTER 5 INTERRUPT CONTROLLER ...
Page 155: ...140 CHAPTER 6 EXTERNAL INTERRUPT AND NMI CONTROLLER ...
Page 197: ...182 CHAPTER 9 PPG Programmable Pulse Generator ...
Page 337: ...322 CHAPTER 13 UART ...
Page 417: ...402 CHAPTER 16 DMAC DMA Controller ...
Page 445: ...430 CHAPTER 17 FLASH MEMORY ...
Page 451: ...436 CHAPTER 18 SERIAL PROGRAMMING CONNECTION ...
Page 493: ...478 APPENDIX F Precautions on Handling ...
Page 494: ...479 INDEX INDEX The index follows on the next page This is listed in alphabetic order ...
Page 507: ...492 INDEX ...
Page 509: ......